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參數(shù)資料
| 型號： | CY25245 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁數(shù)： | 1/11頁 |
| 文件大小： | 116K |
| 代理商： | CY25245 |
Frequency-multiplying, Peak-reducing
EMI Solution
CY25245
Cypress Semiconductor Corporation
Document #: 38-07124 Rev. *A
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised January 7, 2003
Features
Cypress PREMIS SMARTSPREAD family offering
Generates an electromagnetic interference (EMI)
optimized clocking signal at the output
Selectable output frequency range
Single 1.25%, 2.5%, 5%, or 10% down or center spread
output
Integrated loop filter components
Operates with a 3.3 or 5V supply
Low power CMOS design
Available in 20-pin Small Shrunk Outline Package
(SSOP)
Key Specifications
Supply voltages: .......................................V
DD
= 3.3V ± 0.3V
or V
DD
= 5V ± 10%
Frequency range:............................ 13 MHz
≤
F
in
≤
166 MHz
Cycle-to-cycle jitter: ......................................... 250 ps (max)
Output duty cycle: ................................ 40/60% (worst case)
Notes:
1.
2.
Pins marked with ^ are internal pull-down resistors with weak 250 k
.
Pins marked with * are internal pull-up resistors with weak 80 k
.
C
20
19
18
17
16
1
2
3
4
5
6
7
8
9
10
X1
X2
AVDD
MW0^
SDATA
OR1^
SCLK
REFOUT
VDD
GND
IR1*
IR2*
SSOUT
MW1*
GND
14
13
15
11
12
VDD
MW2^
OR2*
SSON#^
GND
Simplified Block Diagram
Pin Configuration
SSOP
Spread Spectrum
Output
CY25245
(EMI suppressed)
3.3V or 5.0V
Oscillator or
Reference Input
Spread Spectrum
CY25245
(EOutput
3.3V or 5.0V
Input
X1
X2
X1
SCLK
SDATA
SDATA
SCLK
Serial Interface
Serial Interface
[1, 2]
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