參數(shù)資料
型號: CY25100ZXIF
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: XO, clock
英文描述: Field- and Factory-Programmable Spread Spectrum Clock Generator for EMI Reduction
中文描述: 200 MHz, OTHER CLOCK GENERATOR, PDSO8
封裝: 4.40 MM, LEAD FREE, TSSOP-8
文件頁數(shù): 2/11頁
文件大?。?/td> 279K
代理商: CY25100ZXIF
CY25100
Document #: 38-07499 Rev. *D
Page 2 of 11
General Description
The CY25100 is a Spread Spectrum Clock Generator (SSCG)
IC used for the purpose of reducing EMI found in today’s
high-speed digital electronic systems.
The device uses a Cypress proprietary PLL and Spread
Spectrum Clock (SSC) technology to synthesize and modulate
the frequency of the input clock. By frequency modulating the
clock, the measured EMI at the fundamental and harmonic
frequencies are greatly reduced. This reduction in radiated
energy can significantly reduce the cost of complying with
regulatory agency (EMC) requirements and improve
time-to-market without degrading system performance.
The CY25100 uses a factory/field-programmable configu-
ration memory array to synthesize output frequency, spread%,
crystal load capacitor, reference clock output on/off, spread
spectrum on/off function and PD#/OE options.
The spread% is programmed to either center spread or down
spread with various spread percentages. The range for center
spread is from ±0.25% to ±2.50%. The range for down spread
is from –0.5% to –5.0%. Contact the factory for smaller or
larger spread % amounts if required.
The input to the CY25100 can be either a crystal or a clock
signal. The input frequency range for crystals is 8–30 MHz,
and for clock signals is 8–166 MHz.
The CY25100 has two clock outputs, REFCLK and SSCLK.
The non-spread spectrum REFCLK output has the same
frequency as the input of the CY25100. The frequency
modulated SSCLK output can be programmed from 3–200
MHz.
The CY25100 products are available in an 8-pin SOIC and
TSSOP packages with commercial and industrial operating
temperature ranges.
Pin Description
Pin
Name
Description
1
2
3
4
VDD
XOUT
XIN/CLKIN
PD#/OE
3.3V power supply
.
Crystal output
. Leave this pin floating if external clock is used.
Crystal input or reference clock input
.
Power-down pin
:
Active LOW
. If PD# = 0, the PLL and Xtal are powered down,
and outputs are weakly pulled low.
Output Enable pin
:
Active HIGH
. If OE = 1, SSCLK and REFCLK are enabled.
User has the option of choosing either PD# or OE function.
Power supply ground
.
Buffered reference output
.
Spread spectrum clock output
.
Spread spectrum control
. 0 = Spread on. 1 = Spread off.
5
6
7
8
VSS
REFCLK
SSCLK
SSON#
Table 1.
Pin
Function
Pin Name
Input
Frequency
XIN and
XOUT
3 and 2
MHz
ENTER DATA ENTER DATA
Total Xtal
Load
Capacitance
XIN and XOUT
Output
Frequency
SSCLK
Spread Percent
(0.5% – 5%,
0.25% Intervals)
SSCLK
Reference
Output
REFOUT
Power-down or
Output Enable
PD#/OE
Frequency
Modulation
SSCLK
Pin#
Unit
Program
Value
3 and 2
pF
7
7
%
6
4
7
MHz
ENTER
DATA
On or Off
ENTER
DATA
Select PD# or OE
ENTER DATA
kHz
31.5
ENTER DATA
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