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參數(shù)資料
| 型號(hào)： | CY2412SC-1 |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | MPEG Clock Generator with VCXO |
| 中文描述： | 54 MHz, VIDEO CLOCK GENERATOR, PDSO8 |
| 封裝： | 0.150 INCH, MS-012, SOIC-8 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 128K |
| 代理商： | CY2412SC-1 |
CY2412
Document #: 38-07227 Rev. *D
Page 3 of 6
Absolute Maximum Conditions
Recommended Operating Conditions
DC Electrical Characteristics
AC Electrical Characteristics
Parameter
V
DD
T
S
T
J
Description
Min.
–0.5
–65
–
Max.
7.0
125
125
V
DD
+ 0.3
V
DD
+ 0.3
Unit
V
°C
°C
V
V
kV
Supply Voltage
Storage Temperature
[3]
Junction Temperature
Digital Inputs
Digital Outputs referred to V
DD
Electrostatic Discharge
V
SS
– 0.3
V
SS
– 0.3
2
Parameter
Description
Min.
3.14
0
Typ.
3.3
Max.
3.47
70
15
Unit
V
°C
pF
MHz
ms
V
DD
T
A
C
LOAD
f
REF
t
PU
Operating Voltage
Ambient Temperature
Max. Load Capacitance
Reference Frequency
Power-up time for all VDDs to reach
minimum specified voltage (power
ramps must be monotonic)
13.5
0.05
500
Parameter
I
OH
I
OL
C
IN
I
IZ
f
XO
V
VCXO
f
VBW
I
DD
Description
Test Conditions
Min.
12
12
Typ.
24
24
Max.
Unit
mA
mA
pF
μ
A
ppm
V
kHz
mA
Output High Current
Output Low Current
Input Capacitance
Input Leakage Current
VCXO pullability range
VCXO input range
VCXO input bandwidth
Supply Current
V
OH
= V
DD
– 0.5, V
DD
= 3.3V
V
OL
= 0.5, V
DD
= 3.3V
7
5
+150
0
V
DD
DC to 200
Sum of Core and Output Current
35
Parameter
[4]
DC
ER
Description
Output Duty Cycle
Rising Edge Rate
Test Conditions
Min.
45
0.8
Typ.
50
1.4
Max.
55
Unit
%
V/ns
Duty Cycle is defined in
Figure 1
, 50% of V
DD
Clock Edge Rate, Measured from 20% to 80%
of V
DD,
C
LOAD
= 15 pF. See
Figure 2
.
Output Clock Edge Rate, Measured from 80% to
20% of V
DD,
C
LOAD
= 15 pF. See
Figure 2
.
Peak to Peak period jitter
EF
Falling Edge Rate
0.8
1.4
V/ns
t
9
t
10
Clock Jitter
PLL Lock Time
100
200
3
ps
ms
Notes:
2. Float X
if X
is externally driven.
3. Rated for ten years.
4. Not 100% tested.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY2412SC-1T | MPEG Clock Generator with VCXO |
| CY2412SC-3 | MPEG Clock Generator with VCXO |
| CY2412SC-3T | MPEG Clock Generator with VCXO |
| CY2412SXC-1 | MPEG Clock Generator with VCXO |
| CY2412SXC-1T | MPEG Clock Generator with VCXO |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY2412SC-1T | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:MPEG Clock Generator with VCXO |
| CY2412SC-2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MISCELLANEOUS CLOCK GENERATOR|SOP|8PIN|PLASTIC |
| CY2412SC-3 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:MPEG Clock Generator with VCXO |
| CY2412SC-3T | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:MPEG Clock Generator with VCXO |
| CY2412SXC-1 | 功能描述:鎖相環(huán) - PLL 1PLL Clk Syn COM RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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