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參數(shù)資料
| 型號(hào)： | CY23S05 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁(yè)數(shù)： | 1/9頁(yè) |
| 文件大?。?/td> | 169K |
| 代理商： | CY23S05 |
Low-Cost 3.3V Spread Aware Zero Delay Buffer
CY23S09
CY23S05
Cypress Semiconductor Corporation
Document #: 38-07296 Rev. *B
3901 North First Street
San Jose
CA 95134
Revised December 22, 2002
408-943-2600
05
Features
10-MHz to 100-/133-MHz operating range, compatible
with CPU and PCI bus frequencies
Zero input-output propagation delay
Multiple low-skew outputs
—Output-output skew less than 250 ps
—Device-device skew less than 700 ps
—One input drives five outputs (CY23S05)
—One input drives nine outputs, grouped as 4 + 4 + 1
(CY23S09)
Less than 200 ps cycle-to-cycle jitter is compatible with
Pentium
-based systems
Test Mode to bypass PLL (CY23S09 only, see Select
Input Decoding table on page 2)
Available in space-saving 16-pin, 150-mil SOIC, 4.4 mm
TSSOP, and 150-mil SSOP ( CY23S09) or 8-pin, 150-mil
SOIC package (CY23S05)
3.3V operation, advanced 0.65
μ
CMOS technology
Spread Aware
Functional Description
The CY23S09 is a low-cost 3.3V zero delay buffer designed to
distribute high-speed clocks and is available in a 16-pin SOIC
package. The CY23S05 is an eight-pin version of the
CY23S09. It accepts one reference input, and drives out five
low-skew clocks. The -1H versions of each device operate at
up to 100-/133-MHz frequencies, and have higher drive than
the -1 devices. All parts have on-chip PLLs that lock to an input
clock on the REF pin. The PLL feedback is on-chip and is
obtained from the CLKOUT pad.
The CY23S09 has two banks of four outputs each, which can
be controlled by the Select inputs as shown in the Select Input
Decoding table on page 2. If all output clocks are not required,
Bank B can be three-stated. The select inputs also allow the
input clock to be directly applied to the outputs for chip and
system testing purposes.
The CY23S09 and CY23S05 PLLs enter a power-down mode
when there are no rising edges on the REF input. In this state,
the outputs are three-stated and the PLL is turned off, resulting
in less than 12.0
μ
A of current draw (for commercial temper-
ature devices) and 25.0
μ
A (for industrial temperature
devices). The CY23S09 PLL shuts down in one additional
case, as shown in the table below.
Multiple CY23S09 and CY23S05 devices can accept the same
input clock and distribute it. In this case, the skew between the
outputs of two devices is guaranteed to be less than 700 ps.
All outputs have less than 200 ps of cycle-to-cycle jitter. The
input to output propagation delay on both devices is
guaranteed to be less than 350 ps, and the output to output
skew is guaranteed to be less than 250 ps.
The CY23S05/CY23S09 is available in two different configu-
rations, as shown in the ordering information on page 6. The
CY23S05-1/CY23S09-1 is the base part. The CY23S05-1H/
CY23S09-1H is the high-drive version of the -1, and its rise
and fall times are much faster than -1.
Block Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
REF
CLKA1
CLKA2
V
DD
GND
CLKB1
CLKB2
S2
CLKOUT
CLKA4
CLKA3
V
DD
GND
CLKB4
CLKB3
S1
SOIC/TSSOP/SSOP
Top View
Pin Configuration
1
2
3
4
5
8
7
6
REF
CLK2
CLK1
GND
V
DD
CLK3
CLKOUT
CLK4
SOIC
Top View
PLL
MUX
Select Input
Decoding
REF
S2
S1
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
CLKOUT
PLL
REF
CLK1
CLK2
CLK3
CLK4
CLKOUT
CY23S09
CY23S05
CY23S09
CY23S05
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY23S09 | Clocks and Buffers |
| CY2410 | Clocks and Buffers |
| CY2411 | Clocks and Buffers |
| CY24115 | Clocks and Buffers |
| CY24119 | Clocks and Buffers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY23S05SC-1 | 制造商:Cypress Semiconductor 功能描述: |
| CY23S05SC-1H | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述:ZERO DELAY BUFFER 3.3 V SPREAD AWARE - Bulk |
| CY23S05SC-1T | 功能描述:鎖相環(huán) - PLL Zero Delay Buffr COM RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY23S05SI-1 | 功能描述:鎖相環(huán) - PLL Zero Delay Buffr IND RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY23S05SI-1T | 功能描述:鎖相環(huán) - PLL Zero Delay Buffer Spread Aware RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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