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參數(shù)資料
| 型號(hào)： | CY2292SXC-XXXT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | Three-PLL General-Purpose EPROM Programmable Clock Generator |
| 中文描述： | 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO16 |
| 封裝： | 0.150 INCH, LEAD FREE, MS-012, SOIC-16 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 189K |
| 代理商： | CY2292SXC-XXXT |
CY2292
Document #: 38-07449 Rev. *B
Page 5 of 11
Electrical Characteristics, Industrial 5.0V
Parameter
V
OH
V
OL
V
IH
V
IL
I
IH
I
IL
I
OZ
I
DD
I
DDS
Description
Conditions
Min.
2.4
Typ.
Max.
Unit
V
V
V
V
μ
A
μ
A
μ
A
mA
μ
A
HIGH-Level Output Voltage
LOW-Level Output Voltage
HIGH-Level Input Voltage
[9]
LOW-Level Input Voltage
[9]
Input HIGH Current
Input LOW Current
Output Leakage Current
V
DD
Supply Current
[10]
Industrial
V
DD
Power Supply Current in
Shutdown Mode
[10]
I
OH
= 4.0 mA
I
OL
= 4.0 mA
Except crystal pins
Except crystal pins
V
IN
= V
DD
– 0.5V
V
IN
= +0.5V
Three-state outputs
V
DD
= V
DD
Max., 5V operation
Shutdown active CY2292I/CY2292FI
0.4
2.0
0.8
10
10
250
110
100
<1
<1
75
10
Electrical Characteristics, Industrial 3.3V
Parameter
V
OH
V
OL
V
IH
V
IL
I
IH
I
IL
I
OZ
I
DD
Description
Conditions
Min.
2.4
Typ.
Max.
Unit
V
V
V
V
μ
A
μ
A
μ
A
mA
HIGH-Level Output Voltage
LOW-Level Output Voltage
HIGH-Level Input Voltage
[9]
LOW-Level Input Voltage
[9]
Input HIGH Current
Input LOW Current
Output Leakage Current
V
DD
Supply Current
[10]
Indus-
trial
V
DD
Power Supply Current in
Shutdown Mode
[10]
I
OH
= 4.0 mA
I
OL
= 4.0 mA
Except crystal pins
Except crystal pins
V
IN
= V
DD
– 0.5V
V
IN
= +0.5V
Three-state outputs
V
DD
= V
DD
Max., 3.3V operation
0.4
2.0
0.8
10
10
250
70
<1
<1
50
I
DDS
Shutdown active
CY2292I/CY2292FI
10
100
μ
A
Switching Characteristics, Commercial 5.0V
Parameter
t
1
Name
Description
Min.
10
Typ.
Max.
13000
Unit
ns
Output Period
Clock output range, 5V
operation
CY2292
(100 MHz)
11.1
(90 MHz)
40%
(76.923 kHz)
13000
(76.923 kHz)
60%
CY2292F
ns
Output Duty Cycle
[11]
Duty cycle for outputs, defined as t
2
÷
t
1[12]
f
OUT
> 66 MHz
Duty cycle for outputs, defined as t
2
÷
t
1[12]
f
OUT
< 66 MHz
Output clock rise time
[13]
Output clock fall time
[13]
Time for output to enter three-state mode
after SHUTDOWN/OE goes LOW
Time for output to leave three-state mode
after SHUTDOWN/OE goes HIGH
Skew delay between any identical or
related outputs
[3, 12, 14]
Frequency transition rate
50%
45%
50%
55%
t
3
t
4
t
5
Rise Time
Fall Time
Output Disable Time
3
5
4
ns
ns
ns
2.5
10
15
t
6
Output Enable Time
10
15
ns
t
7
Skew
< 0.25
0.5
ns
t
8
Notes:
11. XBUF duty cycle depends on XTALIN duty cycle.
12.Measured at 1.4V.
13.Measured between 0.4V and 2.4V.
14.Jitter varies with configuration. All standard configurations sample tested at the factory conform to this limit. For more information on jitter, please refer to the
application note:
Jitter in PLL-Based Systems
.
CPUCLK Slew
1.0
20.0
MHz/ms
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