- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378480 > CY2291SC-XXX (CYPRESS SEMICONDUCTOR CORP) Three-PLL General Purpose EPROM Programmable Clock Generator PDF資料下載
參數(shù)資料
| 型號： | CY2291SC-XXX |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | Three-PLL General Purpose EPROM Programmable Clock Generator |
| 中文描述： | 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO20 |
| 封裝： | 0.300 INCH, MO-119, SOIC-20 |
| 文件頁數(shù)： | 3/13頁 |
| 文件大?。?/td> | 121K |
| 代理商： | CY2291SC-XXX |
CY2291
3
Operation
The CY2291 is a third-generation family of clock generators.
The CY2291 is upwardly compatible with the industry standard
ICD2023 and ICD2028 and continues their tradition by provid-
ing a high level of customizable features to meet the diverse
clock generation needs of modern motherboards and other
synchronous systems.
All parts provide a highly configurable set of clocks for PC
motherboard applications. Each of the four configurable clock
outputs (CLKA
–
CLKD) can be assigned 1 of 30 frequencies in
any combination. Multiple outputs configured for the same or
related
[3]
frequencies will have low (<500 ps) skew, in effect
providing on-chip buffering for heavily loaded signals.
The CY2291 can be configured for either 5V or 3.3V operation.
The internal ROM tables use EPROM technology, allowing full
customization of output frequencies. The reference oscillator
has been designed for 10-MHz to 25-MHz crystals, providing
additional flexibility. No external components are required with
this crystal. Alternatively, an external reference clock of fre-
quency between 1 MHz and 30 MHz can be used. Customers
using the 32-kHz oscillator should connect a 10-M
resistor in
parallel with the 32-kHz crystal.
Output Configuration
The CY2291 has five independent frequency sources on-chip.
These are the 32-kHz oscillator, the reference oscillator, and
three Phase-Locked Loops (PLLs). Each PLL has a specific
function. The System PLL (SPLL) drives the CLKF output and
provides fixed output frequencies on the configurable outputs.
The SPLL offers the most output frequency divider options.
The CPU PLL (CPLL) is controlled by the select inputs
(S0
–
S2) to provide eight user-selectable frequencies with
smooth slewing between frequencies. The Utility PLL (UPLL)
provides the most accurate clock. It is often used for miscella-
neous frequencies not provided by the other frequency sourc-
es.
All configurations are EPROM programmable, providing short
sample and production lead times. Please refer to the applica-
tion note
“
Understanding the CY2291, CY2292, and CY2295
”
for information on configuring the part.
Power Saving Features
The SHUTDOWN/OE input three-states the outputs when
pulled LOW (the 32-kHz clock output is not affected). If system
shutdown is enabled, a LOW on this pin also shuts off the
PLLs, counters, the reference oscillator, and all other active
components. The resulting current on the V
DD
pins will be less
than 50
μ
A (for Commercial Temp. or 100
μ
A for Industrial
Temp.) plus 15
μ
A max. for the 32-kHz subsystem and is typ-
ically 10
μ
A. After leaving shutdown mode, the PLLs will have
to re-lock. All outputs except 32K have a weak pull-down so
that the outputs do not float when three-stated.
[4]
The S2/SUSPEND input can be configured to shut down a
customizable set of outputs and/or PLLs, when LOW. All PLLs
and any of the outputs except 32K can be shut off in nearly any
combination. The only limitation is that if a PLL is shut off, all
outputs derived from it must also be shut off. Suspending a
PLL shuts off all associated logic, while suspending an output
simply forces a three-state condition.
[3]
The CPUCLK can slew (transition) smoothly between 8 MHz
and the maximum output frequency (100 MHz at 5V/80 MHz
at 3.3V for Commercial Temp. parts or 90 MHz at 5V/66.6 MHz
at 3.3V for Industrial Temp. and for field-programmed parts).
This feature is extremely useful in
“
Green
”
PC and laptop ap-
plications, where reducing the frequency of operation can re-
sult in considerable power savings. This feature meets all 486
and Pentium
processor slewing requirements.
CyClocks Software
CyClocks is an easy-to-use application that allows you to con-
figure any one of the EPROM programmable clocks offered by
Cypress. You may specify the input frequency, PLL and output
frequencies, and different functional options. Please note the
output frequency ranges in this data sheet when specifying
them in CyClocks to ensure that you stay within the limits.
CyClocks also has a power calculation feature that allows you
to see the power consumption of your specific configuration.
You can download a copy of CyClocks for free on Cypress
’
s
website at www.cypress.com.
Cypress FTG Programmer
The Cypress Frequency Timing Generator (FTG) Program-
mers is a portable programmer designed to custom program
our family of EPROM Field Programmable Clock Devices. The
FTG programmers connect to a PC serial port and allow users
of CyClocks software to quickly and easily program any of the
CY2291F, CY2292F, CY2071AF, and CY2907F devices. The
ordering code for the Cypress FTG Programmer is CY3670.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY2291SL-XXX | Three-PLL General Purpose EPROM Programmable Clock Generator |
| CY2291 | Three-PLL General Purpose EPROM Programmable Clock Generator |
| CY2291F | Three-PLL General Purpose EPROM Programmable Clock Generator |
| CY2291FI | Three-PLL General Purpose EPROM Programmable Clock Generator |
| CY2300 | Phase-Aligned Clock Multiplier |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY2291SI-XXX | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Three-PLL General Purpose EPROM Programmable Clock Generator |
| CY2291SL224 | 制造商:CYPRESS 功能描述:* |
| CY2291SL-329 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY2291SL-XXX | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Three-PLL General Purpose EPROM Programmable Clock Generator |
| CY2291SXC-161 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。