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參數(shù)資料
| 型號： | CY22394ZXI-XXXT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | -bit AVR Microcontroller with 8K Bytes In- System Programmable Flash |
| 中文描述： | 375 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封裝： | 4.40 MM, LEAD FREE, MO-153, TSSOP-16 |
| 文件頁數(shù)： | 7/19頁 |
| 文件大?。?/td> | 235K |
| 代理商： | CY22394ZXI-XXXT |
CY22393
CY22394
CY22395
Document #: 38-07186 Rev. *B
Page 7 of 19
OscCap[5:0]
This controls the internal capacitive load of the oscillator. The
approximate effective crystal load capacitance is:
Set to zero for external reference clock.
OscDrv[1:0]
These bits control the crystal oscillator gain setting. These
should always be set according to the following table. The
parameters are the Crystal Frequency, Internal Crystal
Parasitic Resistance (available from the manufacturer), and
the OscCap setting during crystal start-up (which occurs when
power is applied, or after shutdown is released). If in doubt,
use the next higher setting.
For external reference, the following table must be used.
Reserved
These bits must be programmed LOW for proper operation of
the device.
Serial Programming Bitmaps — Summary Tables
C
LOAD
6pF
OscCap
0.375pF
×
(
)
+
=
OscCap
Crystal Freq\ R
8–15 MHz
15–20 MHz
20–25 MHz
25–30 MHz
00H–20H
30
00
01
01
10
20H–30H
30
01
01
10
10
30H–40H
30
01
10
10
11
60
01
10
10
10
60
10
10
10
11
60
10
10
11
NA
External Freq (MHz)
OscDrv[1:0]
1–25
00
25–50
01
50–90
10
90–166
11
Addr
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
DivSel
0
1
0
1
–
–
–
–
–
–
–
–
–
–
–
–
b7
b6
b5
b4
b3
b2
b1
b0
ClkA_FS[0]
ClkA_FS[0]
ClkB_FS[0]
ClkB_FS[0]
ClkC_FS[0]
ClkD_FS[0]
ClkA_Div[6:0]
ClkA_Div[6:0]
ClkB_Div[6:0]
ClkB_Div[6:0]
ClkC_Div[6:0]
ClkD_Div[6:0]
ClkD_FS[2:1]
Clk{C,X}_ACAdj[1:0]
ClkX_DCAdj[1]
ClkC_FS[2:1]
Clk{A,B,D,E}_ACAdj[1:0]
Clk{D,E}_DCAdj[1]
ClkB_FS[2:1]
PdnEn
ClkC_DCAdj[1]
ClkA_FS[2:1]
ClkE_Div[1:0]
Clk{A,B}_DCAdj[1]
Xbuf_OE
PLL2_Q[7:0]
PLL2_P[7:0]
Reserved
PLL2_En
PLL2_LF[2:0]
PLL2_PO
PLL2_P[9:8]
PLL3_Q[7:0]
PLL3_P[7:0]
Reserved
PLL3_En
PLL3_LF[2:0]
PLL3_PO
PLL3_P[9:8]
Osc_Drv[1:0]
Osc_Cap[5:0]
Addr
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
S2
(1,0)
000
b7
b6
b5
b4
PLL1_Q[7:0]
PLL1_P[7:0]
PLL1_LF[2:0]
PLL1_Q[7:0]
PLL1_P[7:0]
PLL1_LF[2:0]
PLL1_Q[7:0]
PLL1_P[7:0]
PLL1_LF[2:0]
PLL1_Q[7:0]
PLL1_P[7:0]
PLL1_LF[2:0]
b3
b2
b1
b0
DivSel
PLL1_En
PLL1_PO
PLL1_P[9:8]
001
DivSel
PLL1_En
PLL1_PO
PLL1_P[9:8]
010
DivSel
PLL1_En
PLL1_PO
PLL1_P[9:8]
011
DivSel
PLL1_En
PLL1_PO
PLL1_P[9:8]
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