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參數(shù)資料
| 型號： | CY22393ZI-XXX |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | -bit AVR Microcontroller with 8K Bytes In- System Programmable Flash |
| 中文描述： | 166 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封裝： | 4.40 MM, MO-153, TSSOP-16 |
| 文件頁數(shù)： | 13/19頁 |
| 文件大?。?/td> | 235K |
| 代理商： | CY22393ZI-XXX |
CY22393
CY22394
CY22395
Document #: 38-07186 Rev. *B
Page 13 of 19
3.3V Switching Characteristics
Parameter
1/t
1
Description
Output Frequency
[4, 6]
Conditions
Min.
Typ.
Max.
200
166
400
Unit
MHz
MHz
MHz
Clock output limit, CMOS, Commercial
Clock output limit, CMOS, Industrial
Clock output limit, PECL, Commercial (CY22394
only)
Clock output limit, PECL, Industrial (CY22394
only)
Duty cycle for outputs, defined as t
2
3 t
1
,
Fout<100 MHz, divider>=2,
measured at V
DD
/2
Duty cycle for outputs, defined as t
2
3 t
1
,
Fout>100 MHz or divider = 1,
measured at V
DD
/2
Output clock rise time, 20% to 80% of V
DD
100
125
375
MHz
t
2
Output Duty Cycle
[4, 7]
45%
50%
55%
40%
50%
60%
t
3
Rising Edge Slew
Rate
[4]
Falling Edge Slew
Rate
[4]
Output three-state
Timing
[4]
Clock Jitter
[4, 8]
0.75
1.4
V/ns
t
4
Output clock fall time, 20% to 80% of V
DD
0.75
1.4
V/ns
t
5
Time for output to enter or leave three-state
mode after SHUTDOWN/OE switches
Peak-to-peak period jitter, CLK outputs
measured at V
DD
/2
150
300
ns
t
6
400
ps
v
7
P+/P– Crossing Point
[4]
Crossing point referenced to Vdd/2, balanced
resistor network (CY22394 only)
P+/P– Jitter
[4, 8]
Peak-to-peak period jitter, P+/P– outputs
measured at crossing point (CY22394 only)
Lock Time
[4]
PLL Lock Time from Power-up
–0.2
0
0.2
V
t
8
200
ps
t
9
1.0
3
ms
2.5V Switching Characteristics
(CY22395 only)
[5]
Parameter
1/t
1_2.5
t
2_2.5
Description
Conditions
Min.
Typ.
Max.
133
60%
Unit
MHz
Output Frequency
[4, 6]
Output Duty Cycle
[4, 7]
Clock output limit, LVCMOS
Duty cycle for outputs, defined as t
2
÷
t
1
measured at LV
DD
/2
Output clock rise time, 20% to 80% of LV
DD
40%
50%
t
3_2.5
t
4_2.5
Rising Edge Slew Rate
[4]
Falling Edge Slew Rate
[4]
Output clock fall time, 20% to 80% of LV
DD
0.5
0.5
1.0
1.0
V/ns
V/ns
Switching Waveforms
Notes:
6. Guaranteed to meet 20%–80% output thresholds, duty cycle, and crossing point specifications.
7. Reference Output duty cycle depends on XTALIN duty cycle.
8. Jitter varies significantly with configuration. Reference Output jitter depends on XTALIN jitter and edge rate.
t
1
OUTPUT
t
2
t
3
t
4
All Outputs, Duty Cycle and Rise/Fall Time
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY22393ZI-XXXT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Three-PLL Serial-Programmable Flash-Programmable Clock Generator |
| CY22393ZXC-515 | 制造商:Cypress Semiconductor 功能描述: |
| CY22393ZXC-515T | 制造商:Cypress Semiconductor 功能描述: |
| CY22393ZXC-518 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY22393ZXC-519 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 3-PLL Serial-Program FL-Program Clk Gen RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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