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參數(shù)資料
| 型號(hào)： | CY22393FXIT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | -bit AVR Microcontroller with 8K Bytes In- System Programmable Flash |
| 中文描述： | 166 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封裝： | 4.40 MM, LEAD FREE, MO-153, TSSOP-16 |
| 文件頁數(shù)： | 5/19頁 |
| 文件大?。?/td> | 235K |
| 代理商： | CY22393FXIT |
CY22393
CY22394
CY22395
Document #: 38-07186 Rev. *B
Page 5 of 19
Be aware that adjusting the frequency of the reference will
affect all frequencies on all PLLs in a similar manner since all
frequencies are derived from the single reference.
Output Configuration
Under normal operation there are four internal frequency
sources that may be routed via a programmable cross point
switch to any of the four programmable 7-bit output dividers.
The four sources are: reference, PLL1, PLL2, and PLL3. The
following is a description of each output.
CLKA’s output originates from the cross point switch and goes
through a programmable 7-bit post divider. The 7-bit post
divider derives its value from one of two programmable
registers. See the section on General-Purpose Inputs for more
information.
CLKB’s output originates from the cross point switch and goes
through a programmable 7-bit post divider. The 7-bit post
divider derives its value from one of two programmable
registers. See the section on General-Purpose Inputs for more
information.
CLKC’s output originates from the cross point switch and goes
through a programmable 7-bit post divider. The 7-bit post
divider derives its value from one programmable register.
CLKD’s output originates from the cross point switch and goes
through a programmable 7-bit post divider. The 7-bit post
divider derives its value from one programmable register. For
the CY22394, CLKD is brought out as the complimentary
version of a LV PECL Clock referenced to CLKE, bypassing
both the cross point switch and 7-bit post divider.
CLKE’s output originates from PLL1 and goes through a post
divider that may be programmed to /2, /3, or /4. For the
CY22394, CLKE is brought out as an LV PECL Clock,
bypassing the post divider.
XBUF is simply the buffered reference.
The Clock outputs have been designed to drive a single point
load with a total lumped load capacitance of 15 pF. While
driving multiple loads is possible with the proper termination it
is generally not recommended.
Power-Saving Features
The SHUTDOWN/OE input three-states the outputs when
pulled LOW. If system shutdown is enabled, a LOW on this pin
also shuts off the PLLs, counters, reference oscillator, and all
other active components. The resulting current on the V
DD
pins will be less than 5 mA (typical). After leaving shutdown
mode, the PLLs will have to relock.
The S2/SUSPEND input can be configured to shut down a
customizable set of outputs and/or PLLs, when LOW. All PLLs
and any of the outputs can be shut off in nearly any combi-
nation. The only limitation is that if a PLL is shut off, all outputs
derived from it must also be shut off. Suspending a PLL shuts
off all associated logic, while suspending an output simply
forces a three-state condition.
With the serial interface, each PLL and/or output can be
individually disabled. This provides total control over the power
savings.
Improving Jitter
Jitter Optimization Control is useful in mitigating problems
related to similar clocks switching at the same moment,
causing excess jitter. If one PLL is driving more than one
output, the negative phase of the PLL can be selected for one
of the outputs (CLKA–CLKD). This prevents the output edges
from aligning, allowing superior jitter performance.
Power Supply Sequencing
For parts with multiple V
DD
pins, there are no power supply
sequencing requirements. The part will not be fully operational
until all V
DD
pins have been brought up to the voltages
specified in the “Operating Conditions” table.
All grounds should be connected to the same ground plane.
CyClocksRT Software
CyClocksRT is our second-generation software application
that allows users to configure this family of devices. The
easy-to-use interface offers complete control of the many
features of this family including, but not limited to, input
frequency, PLL and output frequencies, and different
functional options. Data sheet frequency range limitations are
checked and performance tuning is automatically applied.
CyClocksRT also has a power estimation feature that allows
the user to see the power consumption of a specific configu-
ration. You can download a free copy of CyberClocks that
includes CyClocksRT for free on Cypress’s web site at
www.cypress.com
CyClocksRT is used to generate P, Q, and divider values used
in serial programming. There are many internal frequency
rules which are not documented in this data sheet, but are
required for proper operation of the device. These rules can
be checked by using the latest version of CyClocksRT.
Junction Temperature Limitations
It is possible to program this family such that the maximum
Junction Temperature rating is exceeded. The package q
JA
is
115 °C/W. Use the CyClocksRT power estimation feature to
verify that the programmed configuration meets the Junction
Temperature and Package Power Dissipation maximum
ratings.
Dynamic Updates
The output divider registers are not synchronized with the
output clocks. Changing the divider value of an active output
will likely cause a glitch on that output.
PLL P and Q data is spread between three bytes. Each byte
becomes active on the acknowledge for that byte, so changing
P and Q data for an active PLL will likely cause the PLL try to
lock on an out-of-bounds condition. For this reason, it is
recommended that the PLL being programmed be turned off
during the update. This can be done by setting the PLL*_En
bit LOW.
PLL1, CLKA, and CLKB each have multiple registers
supplying data. Programming these resources can be accom-
plished safely by always programming an inactive register,
and then transitioning to that register. This allows these
resources to stay on during programming.
The serial interface is active even with the SHUTDOWN/OE
pin LOW as the serial interface logic uses static components
and is completely self-timed. The part will not meet the I
DDS
current limit with transitioning inputs.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| CY22393KFXC | 制造商:Cypress Semiconductor 功能描述: |
| CY22393KFXI | 制造商:Cypress Semiconductor 功能描述: |
| CY22393KZXC-518 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 3-PLL Serial-Program FL-Program Clk Gen RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| CY22393KZXC-519 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 3-PLL Serial-Program FL-Program Clk Gen RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| CY22393KZXC-524 | 制造商:Cypress Semiconductor 功能描述: |
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