參數(shù)資料
型號(hào): CY22392FXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: XO, clock
英文描述: Three-PLL General Purpose FLASH Programmable Clock Generator
中文描述: 200 MHz, OTHER CLOCK GENERATOR, PDSO16
封裝: 4.40 MM, MO-153, TSSOP-16
文件頁數(shù): 4/8頁
文件大小: 157K
代理商: CY22392FXC
CY22392
Document #: 38-07013 Rev. *D
Page 4 of 8
Improving Jitter
Jitter Optimization Control is useful in mitigating problems
related to similar clocks switching at the same moment,
causing excess jitter. If one PLL is driving more than one
output, the negative phase of the PLL can be selected for one
of the outputs (CLKA–CLKD). This prevents the output edges
from aligning, allowing superior jitter performance.
Power Supply Sequencing
For parts with multiple V
DD
pins, there are no power supply
sequencing requirements. The part will not be fully operational
until all V
DD
pins have been brought up to the voltages
specified in the “Operating Conditions” table.
All grounds should be connected to the same ground plane.
CyClocksRT Software
CyClocksRT is our second-generation application that allows
users to configure this device. The easy-to-use interface offers
complete control of the many features of this family including
input frequency, PLL and output frequencies, and different
functional options. Data sheet frequency range limitations are
checked and performance tuning is automatically applied.
CyClocksRT also has a power estimation feature that allows
you to see the power consumption of your specific configu-
ration. You can download a copy of CyClocksRT for free on
Cypress’s web site at www.cypress.com.
Junction Temperature Limitations
It is possible to program the CY22392 such that the maximum
Junction Temperature rating is exceeded. The package
θ
JA
is
115 C/W. Use the CyClocksRT power estimation feature to
verify that the programmed configuration meets the Junction
Temperature and Package Power Dissipation maximum
ratings.
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Supply Voltage ...............................................–0.5V to +7.0V
DC Input Voltage ............................–0.5V to + (AV
DD
+ 0.5V)
Storage Temperature ................................. –65
°
C to +125
°
C
Junction Temperature...................................................125
°
C
Data Retention @ Tj = 125
°
C.................................>10 years
Maximum Programming Cycles .......................................100
Package Power Dissipation...................................... 350 mW
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ..........................................
2000V
Latch up (per JEDEC 17) .................................... > ±200 mA
Operating Conditions
[1]
Parameter
Description
Min.
Typ.
Max.
Unit
V
DD
/AV
DD
T
A
Supply Voltage
3.135
3.3
3.465
V
°
C
°
C
Commercial Operating Temperature, Ambient
0
+70
Industrial Operating Temperature, Ambient
–40
+85
C
LOAD_OUT
f
REF
Max. Load Capacitance
15
pF
External Reference Crystal
External Reference Clock
[2]
, Commercial
External Reference Clock
[2]
, Industrial
8
30
MHz
1
166
MHz
1
150
MHz
t
PU
Power-up time for all VDD's to reach minimum specified voltage
(power ramps must be monotonic)
0.05
500
ms
Notes:
1. Unless otherwise noted, Electrical and Switching Characteristics are guaranteed across these operating conditions.
2. External input reference clock must have a duty cycle between 40% and 60%, measured at V
DD
/2.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY22392FXCKN 制造商:Cypress Semiconductor 功能描述:
CY22392FXCT 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 3-PLL Clk Syn COM RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
CY22392FXI 功能描述:鎖相環(huán) - PLL 3-PLL Clk Syn IND RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
CY22392FXIKN 制造商:Cypress Semiconductor 功能描述:
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