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參數(shù)資料
| 型號(hào)： | CY22381SXC-JWK |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | MS (MIL-C-5015)/97 SERIES 3108B SPLIT SHELL ANGLE PLUGS, RIGHT ANGLE BODY STYLE, SOLDER TERMINATION, 18 SHELL SIZE, 18-1 INSERT ARRANGEMENT, PLUG GENDER, 10 CONTACTS |
| 中文描述： | 三鎖相環(huán)通用閃存可編程時(shí)鐘發(fā)生器 |
| 文件頁(yè)數(shù)： | 4/8頁(yè) |
| 文件大?。?/td> | 143K |
| 代理商： | CY22381SXC-JWK |
CY22381
Document #: 38-07012 Rev. *D
Page 4 of 8
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Supply Voltage...............................................–0.5V to +7.0V
DC Input Voltage..............................–0.5V to + (V
DD
+ 0.5V)
Storage Temperature ..................................–65°C to +125°C
Junction Temperature.................................................. 125°C
Data Retention @ Tj = 125°C................................> 10 years
Maximum Programming Cycles........................................100
Package Power Dissipation......................................250 mW
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ...........................
≥
2000V
Latch up (per JEDEC 17) ....................................
≥
±200 mA
Operating Conditions
[1]
Parameter
V
DD
T
A
Description
Min.
3.135
0
–40
–
8
1
1
0.05
Typ.
3.3
–
–
–
–
–
–
–
Max.
3.465
+70
+85
15
30
166
150
500
Unit
V
°C
°C
pF
MHz
MHz
MHz
ms
Supply Voltage
Commercial Operating Temperature, Ambient
Industrial Operating Temperature, Ambient
Max. Load Capacitance
External Reference Crystal
External Reference Clock
[2]
, Commercial
External Reference Clock
[2]
, Industrial
Power-up time for all VDD's to reach minimum specified voltage
(power ramps must be monotonic)
C
LOAD_OUT
f
REF
t
PU
Electrical Characteristics
Parameter
I
OH
I
OL
C
XTAL_MIN
C
XTAL_MAX
C
IN
V
IH
V
IL
I
IH
I
IL
I
OZ
I
DD
Description
Conditions
Min.
12
12
–
–
–
70%
–
–
–
–
–
–
–
Typ.
24
24
6
30
7
–
–
<1
<1
–
35
70
5
Max.
–
–
–
–
–
–
30%
10
10
10
–
–
20
Unit
mA
mA
pF
pF
pF
V
DD
V
DD
μ
A
μ
A
μ
A
mA
mA
μ
A
Output High Current
[3]
Output Low Current
[3]
Crystal Load Capacitance
[3]
Crystal Load Capacitance
[3]
Input Pin Capacitance
[3]
HIGH-level Input Voltage
LOW-level Input Voltage
Input HIGH Current
Input LOW Current
Output Leakage Current
Total Power Supply Current
V
OH
= V
DD
– 0.5, V
DD
= 3.3 V
V
OL
= 0.5V, V
DD
= 3.3 V
Capload at minimum setting
Capload at maximum setting
Except crystal pins
CMOS levels,% of V
DD
CMOS levels,% of V
DD
V
IN
= V
DD
– 0.3 V
V
IN
= +0.3 V
Three-state outputs
3.3 V Power Supply; 3 outputs @ 50 MHz
3.3 V Power Supply; 3 outputs @ 166 MHz
Shut-down active
I
DDS
Total Power Supply Current in
Shutdown Mode
Notes:
1. Unless otherwise noted, Electrical and Switching Characteristics are guaranteed across these operating conditions.
2. External input reference clock must have a duty cycle between 40% and 60%, measured at V
DD
/2.
3. Guaranteed by design, not 100% tested.
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