參數(shù)資料
型號： CY22313ZC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： XO, clock
英文描述： Non-Insulated Male Tab
中文描述： 393.216 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO24
封裝： 4.40 MM, TSSOP-24
文件頁數(shù)： 4/9頁
文件大小： 165K
代理商： CY22313ZC
CY22313
Document #: 38-07434 Rev. *E
Page 4 of 9
Switching Characteristics
[3]
Parameter
F
PPM
Description
Conditions
Min.
Typ.
±5
±2
50
1.2
0.5
1.2
0.5
Max.
±10
±5
55
4.0
2.5
4.0
2.5
400
100
Unit
PPM
PPM
%
V/ns
V/ns
V/ns
V/ns
ps
ps
Frequency Error
Part to Part, does not include PCB variation
[8]
Over commercial temperature range
[9]
Duty cycle for all outputs, measured at V
DD
/2
DC
t
3_54, 2.5
t
3_54, 1.675
t
4_54, 2.5
t
4_54, 1.675
t
CR
, t
CF
t
CR-CF
Output Duty Cycle
54MOUT Rising Edge Slew Rate 20% to 80% of V
DD54
, V
DD54
= 2.5V
54MOUT Rising Edge Slew Rate 20% to 80% of V
DD54
, V
DD54
= 1.675V
54MOUT Falling Edge Slew Rate 80% to 20% of V
DD54
, V
DD54
= 2.5V
54MOUT Falling Edge Slew Rate 80% to 20% of V
DD54
, V
DD54
= 1.675V
CLK/CLKB Rise and Fall Times
20% to 80% of output voltage
CLK/CLKB Rise and Fall
Difference
[10]
Lock Time
[11]
PLL lock time from power-up
45
0.75
0.35
0.75
0.35
160
20% to 80% of output voltage
t
5
1.0
3.0
ms
Phase Noise Specifications
Parameter
Description
Conditions
Min.
Typ.
–95
–92
Max.
Unit
dBc
dBc
Phase Noise
Phase Noise
54 MHz at 10-kHz offset
53.946 MHz at 10-kHz offset
Jitter Specifications
[3]
Parameter
t
6_LCLK
t
6_54, 2.5
Description
Conditions
Typ.
Max.
250
150
150
250
250
250
400
400
50
70
300
400
50
70
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
LCLK Jitter
[12]
54MOUT Jitter
[12]
Cycle-Cycle Jitter – 9.216 MHz
Cycle-Cycle Jitter – 54 MHz, V
DD
= 2.5V
Cycle-Cycle Jitter – 53.946 MHz, V
DD
= 2.5V
Cycle-Cycle Jitter – 54 MHz, V
DD
= 1.675V
Cycle-Cycle Jitter – 53.946 MHz, V
DD
= 1.675V
1000 Cycle Jitter – 9.216 MHz
1000 Cycle Jitter – 54 MHz,
1000 Cycle Jitter – 53.946 MHz,
Cycle-Cycle Jitter, 1–6 Cycles, 400 MHz
Cycle-Cycle Jitter, 1–6 Cycles, 300 MHz
Long-term Jitter, 400 MHz
Long-term Jitter, 300 MHz
Cycle-Cycle Duty Cycle Error, 400 MHz
Cycle-Cycle Duty Cycle Error, 300 MHz
t
6_54, 1.675
t
7_LCLK
t
7_54
LCLK 1000 Cycle Jitter
[13]
54MOUT 1000 Cycle Jitter
[13]
t
8
CLK/CLKB 1–6 Cycle Jitter
[14]
t
9
CLK/CLKB Long-term Jitter
[15]
t
10
CLK/CLKB Duty Cycle Error
[16]
Notes:
8.
9.
10. Crystal should not be heated for this test, only IC.
11.
Lock Time shown in
Figure 2.
12. LCLK and 54MOUT Cycle-Cycle Jitter shown in
Figure 3.
13. LCLK and 54MOUT 1000 Cycle Jitter shown in
Figure 4.
14. CLK/CLKB 1-6 Cycle Jitter specification is absolute value of worst case deviation, and is shown in
Figure 5
and
Figure 6
.
15. CLK/CLKB Long Term Jitter shown in
Figure 7
.
16. CLK/CLKB Duty Cycle Error shown in
Figure 8
.
Tested across three lots on same board, PCB boards can vary more than ± 5 PPM.
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