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參數資料
| 型號： | CY2220PVC-1 |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | 133-MHz Spread Spectrum Clock Synthesizer/Driver With Differential CPU Outputs |
| 中文描述： | 133 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | SSOP-56 |
| 文件頁數： | 1/11頁 |
| 文件大?。?/td> | 128K |
| 代理商： | CY2220PVC-1 |
133-MHz Spread Spectrum Clock Synthesizer/Driver
with Differential CPU Outputs
CY2220
Cypress Semiconductor Corporation
Document #: 38-07206 Rev. *A
3901 North First Street
San Jose
CA 95134
Revised December 30, 2002
408-943-2600
0
Features
Benefits
Compliant to Intel
CK00 Clock Synthesizer/Driver
Specifications
Multiple output clocks at different frequencies
—
Four pairs of differential CPU outputs, up to 133 MHz
—
Ten synchronous PCI clocks
—
Two Memory Reference clocks, 180 degrees out of
phase
—
Four AGP and Hub Link clocks at 66 MHz
—
Two 48-MHz clocks
—
Two reference clocks at 14.318 MHz
Spread Spectrum clocking
—
31 kHz modulation frequency
—
Default is
–
0.6%, which is recommended by Intel
Power-down features
Three Select inputs
Low-skew and low-jitter outputs
OE and Test Mode support
56-pin SSOP package
Supports next generation Pentium
processors using differen-
tial clock drivers
Motherboard clock generator
—
Support Multiple CPUs and a chipset
—
Support for PCI slots and chipset
—
Drives up to two Direct Rambus
Clock Generators
(DRCG)
—
Supports USB host controller and SuperI/O chip
—
Supports ISA slots and I/O chip
Enables reduction of EMI and overall system cost
Enables ACPI compliant designs
Supports up to eight CPU clock frequencies
Meets tight system timing requirements at high frequency
Enables ATE and
“
bed of nails
”
testing
Widely available, standard package enables lower cost
Intel and Pentium are registered trademarks of Intel Corporation.
Direct Rambus is a trademark of Rambus, Inc.
Logic Block Diagram
EPROM
XTALOUT
XTALIN
14.318
MHz
OSC.
MemRef, MemRefB
SELA
SELB
SEL133
CPU
PLL
REFCLK [0
–
1]
CPUCLK [0
–
3]
PCICLK [0
–
9] (33.33 MHz)
SYS
PLL
USBCLK [0-1] (48 MHz)
MultSel1
MultSel0
CPUCLKB [0
–
3]
Divider
and
Stop Logic
SPREAD
3V66 [0
–
3] (66.67 MHz)
SSOP
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
33
32
31
30
29
36
35
34
V
SSREF
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
45
44
43
42
41
37
38
39
40
48
47
46
REFCLK0/MultSel_0
REFCLK1/MultSel_1
V
DDREF
XTALIN
XTALOUT
49
52
51
50
53
56
55
54
V
DDPCI
PCICLK_6
PCICLK_7
V
SSPCI
Sel133
V
SSUSB
3V66_1
3V66_2
V
SS3V66
V
SS3V66
V
SSCPU
I
REF
CPUCLK_2B
V
SSCPU
V
SSMEM
SPREAD
V
SSPCI
PCICLK_5
V
DDPCI
PCICLK_8
USBCLK1/SelB
AV
SS
V
DD3V66
V
DDCPU
CPUCLK_0
CPUCLK_3B
V
DDCPU
V
DDMEM
MemRef
PCICLK_0
PCICLK_1
PCICLK_2
PCICLK_3
V
SSPCI
PCICLK_4
PCICLK_9
V
DDPCI
USBCLK0/SelA
3V66_3
AV
DD
CPUCLK_0B
CPUCLK_1B
CPUCLK_1
CPUCLK_2
CPUCLK_3
MemRefB
V
DDUSB
PWR_DWN
3V66_0
V
DD3V66
C
PWR_DWN
Pin Configuration
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相關代理商/技術參數 |
參數描述 |
|---|---|
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