參數(shù)資料
型號: CY2077ZC-XXX
英文描述: MISCELLANEOUS CLOCK GENERATOR|TSSOP|8PIN|PLASTIC
中文描述: 雜項(xiàng)時鐘發(fā)生器| TSSOP封裝| 8引腳|塑料
文件頁數(shù): 9/12頁
文件大?。?/td> 305K
代理商: CY2077ZC-XXX
CY2077
9
Typical Rise Time
[6]
and Fall Time
[6]
Trends for CY2077
Rise/Fall time vs. V
DD
over Temperatures
Rise/Fall time vs. Output Loads over Temperatures
Rise Time vs. VDD -- CMOS duty Cycle
Cload = 15pF
1.00
1.20
1.40
1.60
1.80
2.00
2.7
3.0
3.3
3.6
3.9
VDD (V)
R
-40C
25C
85C
Fall Time vs. VDD -- CMOS duty Cycle
Cload = 15pF
1.00
1.20
1.40
1.60
1.80
2.00
2.7
3.0
3.3
3.6
3.9
VDD (V)
F
-40C
25C
85C
Rise Time vs. VDD -- TTL duty Cycle
Cload = 15pF
0.20
0.30
0.40
0.50
0.60
0.70
4.0
4.5
5.0
5.5
6.0
VDD (V)
R
-40C
25C
85C
Fall Time vs. VDD -- TTL duty Cycle
Cload = 15pF
0.20
0.30
0.40
0.50
0.60
0.70
4.0
4.5
5.0
5.5
6.0
VDD (V)
F
-40C
25C
85C
Rise Time vs. CLoad over Temperature
VDD = 3.3v, CMOS output
1.00
1.20
1.40
1.60
1.80
2.00
2.20
10
15
20
25
30
35
Cload (pF)
R
-40C
25C
85C
Fall Tim e vs. CLoad over Tem perature
VDD = 3.3v, CMOS output
1.00
1.20
1.40
1.60
1.80
2.00
10
15
20
25
30
35
Cload (pF)
F
-40C
25C
85C
Note:
6.
Rise/Fall Time for CMOS output is measured between 1.2 V
DD
and 0.8 V
DD
. Rise/Fall Time for TTL output is measured between 0.8V and 2.0V.
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