參數(shù)資料
型號: CY14E256L
廠商: Cypress Semiconductor Corp.
英文描述: 256-Kbit (32K x 8) nvSRAM
中文描述: 256千位(32K的× 8)非易失
文件頁數(shù): 1/16頁
文件大?。?/td> 785K
代理商: CY14E256L
PRELIMINARY
256-Kbit (32K x 8) nvSRAM
CY14E256L
Cypress Semiconductor Corporation
Document #: 001-06968 Rev. *C
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised November 28, 2006
Features
25 ns and 45 ns Access Times
“Hands-off” Automatic
STORE
on Power Down with
external 68
μ
F
capacitor
STORE
to QuantumTrap
Nonvolatile Elements is
initiated by Software, Hardware or Autostore
on
Power-down
RECALL
to SRAM Initiated by Software or Power-up
Infinite
READ, WRITE
and
RECALL
Cycles
15 mA Typical I
CC
at 200 ns Cycle Time
1,000,000
STORE
Cycles to QuantumTrap
100-Year Data Retention to QuantumTrap
Single 5V Operation +10%
Commercial Temperature
SOIC Package
RoHS Compliance
Functional Description
The Cypress CY14E256L is a fast static RAM with a nonvol-
atile element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
Infinite read and write cycles, while independent, nonvolatile
data resides in the highly reliable QuantumTrap cell. Data
transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down.
On power-up, data is restored to the SRAM (the RECALL
operation) from the nonvolatile memory. Both the STORE and
RECALL operations are also available under software control.
A hardware STORE may be initiated with HSB pin.
Logic Block Diagram
STORE/
RECALL
CONTROL
POWER
CONTROL
SOFTWARE
DETECT
STATIC RAM
ARRAY
512 X 512
Quantum Trap
512 X 512
STORE
RECALL
COLUMN I/O
COLUMN DEC
R
I
OE
CE
WE
HSB
V
CC
V
CAP
A
13
-
A
0
A
0
A
1
A
2
A
3
A
4
A
10
A
5
A
6
A
7
A
8
A
9
A
11
A
12
A
13
A
14
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
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