參數(shù)資料
型號: CY14B104N
廠商: Cypress Semiconductor Corp.
英文描述: 4-Mbit (512K x 8/256K x 16) nvSRAM
中文描述: 4兆位(為512k × 8/256K × 16)非易失
文件頁數(shù): 1/21頁
文件大?。?/td> 371K
代理商: CY14B104N
4-Mbit (512K x 8/256K x 16) nvSRAM
PRELIMINARY
CY14B104L/CY14B104N
Cypress Semiconductor Corporation
Document #: 001-07102 Rev. *E
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised June 29, 2007
Feature
15 ns, 25 ns, and 45 ns access times
Internally organized as 512K x 8 or 256K x 16
Hands-off automatic
STORE
on power down with only a
small capacitor
STORE
to
QuantumTrap
nonvolatile elements is initiated
by software, device pin or Autostore
on power down
RECALL
to SRAM initiated by software or power up
Infinite read, write, and recall cycles
8 mA typical I
CC
at 200 ns cycle time
200,000
STORE
cycles to
QuantumTrap
20 year data retention
Single 3V +20%, –10% operation
Commercial and industrial temperatures
FBGA and TSOP - II packages
RoHS compliance
Functional Description
The Cypress CY14B104L/CY14B104N is a fast static RAM,
with a nonvolatile element in each memory cell. The memory
is organized as 512K words of 8 bits each or 256K words of 16
bits each. The embedded nonvolatile elements incorporate
QuantumTrap technology producing the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and
write cycles, while independent, nonvolatile data resides in the
highly reliable QuantumTrap cell. Data transfers from the
SRAM to the nonvolatile elements (the STORE operation)
takes place automatically at power down. On power up, data
is restored to the SRAM (the RECALL operation) from the
nonvolatile memory. Both the STORE and RECALL
operations are also available under software control.
Logic Block Diagram
A
0
- A
18
Address
WE
OE
CE
V
CC
V
SS
V
CAP
DQ0 - DQ15
HSB
CY14B104L/CY14B104N
BHE
BLE
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