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| 型號(hào)： | CY14B104L-ZS25XIT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 4-Mbit (512K x 8/256K x 16) nvSRAM |
| 中文描述： | 512K X 8 NON-VOLATILE SRAM, 25 ns, PDSO44 |
| 封裝： | ROHS COMPLIANT, TSOP2-44 |
| 文件頁數(shù)： | 21/21頁 |
| 文件大?。?/td> | 371K |
| 代理商： | CY14B104L-ZS25XIT |
CY14B104L/CY14B104N
PRELIMINARY
Document #: 001-07102 Rev. *E
Page 21 of 21
Document History Page
Document Title: CY14B104L/CY14B104N 1-Mbit (128K x 8) nvSRAM
Document Number: 001-07102
Issue
Date
**
431039
See ECN
*A
489096
See ECN
REV.
ECN NO.
Orig. of
Change
TUP
TUP
Description of Change
New Data Sheet
Removed 48 SSOP Package
Added 48 FBGA and 54 TSOPII Packages
Updated Part Numbering Nomenclature and Ordering Information
Added Soft Sequence Processing Time Waveform
Removed 35 ns speed bin
Added 55 ns speed bin. Updated AC table for the same
Changed “Unlimited” read/write to “infinite” read/write
Features section: Changed typical I
CC
at 200-ns cycle time to 8 mA
Changed STORE cycles from 500K to 200K cycles
Shaded Commercial grade in operating range table
Modified Icc/Isb specs
48 FBGA package nomenclature changed from BW to BV
Modified part nomenclature table. Changes reflected in the ordering infor-
mation table
Removed 55ns speed bin
Changed pinout for 44TSOPII and 54TSOPII packages
Changed I
SB
to 1mA
Changed I
CC4
to 3mA
Changed V
CAP
min to 35
μ
F
Changed V
IH
max to Vcc + 0.5V
Changed t
STORE
to 15ms
Changed t
PWE
to 10ns
Changed t
SCE
to 15ns
Changed t
SD
to 5ns
Changed t
AW
to 10ns
Removed t
HLBL
Added Timing Parameters for BHE and BLE - t
DBE
, t
LZBE
, t
HZBE
, t
BW
Removed min specification for Vswitch
Changed t
GLAX
to 1ns
Added t
DELAY
max of 70us
Changed t
SS
specification from 70us min to 70us max
Changed the datasheet from Advance information to Preliminary
48 FBGA package code changed from BV to BA
Removed 48 FBGA package in X8 configuration in ordering information.
Changed t
DBE
to 10ns in 15ns part
Changed t
HZBE
in 15ns part to 7ns and in 25ns part to10ns
Changed t
BW
in 15ns part to 15ns and in 25ns part to 20ns
Changed t
GLAX
to t
GHAX
Changed the value of I
CC3
to 25mA
Changed the value of t
AW
in 15ns part to15ns
Changed A
18
and A
19
Pins in FBGA Pin Configuration to NC
Included all the information for 45ns part in this datasheet
*B
499597
See ECN
PCI
*C
517793
See ECN
TUP
*D
774001
See ECN
UHA
*E
914220
See ECN
UHA
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY14B104L-ZS45XCT | 4-Mbit (512K x 8/256K x 16) nvSRAM |
| CY14B104L-ZS45XI | 4-Mbit (512K x 8/256K x 16) nvSRAM |
| CY14B104L-ZS45XIT | 4-Mbit (512K x 8/256K x 16) nvSRAM |
| CY14B104L-ZSP15XCT | 4-Mbit (512K x 8/256K x 16) nvSRAM |
| CY14B104L-ZSP15XI | 4-Mbit (512K x 8/256K x 16) nvSRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY14B104L-ZS45XC | 功能描述:NVRAM 4 Mbit (512K x 8) 45ns nvSRAM RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲(chǔ)容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時(shí)間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| CY14B104L-ZS45XCES | 功能描述:NVRAM nvSRAM 512Kx8 3V RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲(chǔ)容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時(shí)間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| CY14B104L-ZS45XCT | 功能描述:NVRAM 4 Mbit (512K x 8) 45ns nvSRAM RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲(chǔ)容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時(shí)間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| CY14B104L-ZS45XI | 功能描述:NVRAM 4 Mbit (512K x 8) 45ns nvSRAM RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲(chǔ)容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時(shí)間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| CY14B104L-ZS45XIT | 功能描述:NVRAM 512Kb x 8, 2.7-3.6V 45ns nvSRAM RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲(chǔ)容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時(shí)間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
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