參數(shù)資料
型號: CY14B101L
廠商: Cypress Semiconductor Corp.
英文描述: 1-Mbit (128K x 8) nvSRAM
中文描述: 1兆位(128K的× 8)非易失
文件頁數(shù): 1/18頁
文件大?。?/td> 1085K
代理商: CY14B101L
1-Mbit (128K x 8) nvSRAM
PRELIMINARY
CY14B101L
Cypress Semiconductor Corporation
Document #: 001-06400 Rev. *E
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised January 24, 2007
Features
25 ns, 35 ns, and 45 ns access times
“Hands-off” automatic
STORE
on power down with only a
small capacitor
STORE
to QuantumTrap
TM
nonvolatile elements is initiated
by software, device pin, or Autostore
TM
on power down
RECALL
to SRAM initiated by software or power up
Infinite
READ, WRITE,
and
RECALL
cycles
10 mA typical I
CC
at 200 ns cycle time
200,000
STORE
cycles to quantum trap
20-year data retention @
55
°
C
Single 3V operation
+20
%,
–10%
Commercial and industrial temperature
SOIC and SSOP packages
RoHS compliance
Functional Description
The Cypress CY14B101L is a fast static RAM with a
nonvolatile element in each memory cell. The embedded
nonvolatile elements incorporate QuantumTrap technology
producing, the world’s most reliable nonvolatile memory. The
SRAM provides infinite read and write cycles; while
independent, nonvolatile data resides in the highly reliable
QuantumTrap cell. Data transfers from the SRAM to the
nonvolatile elements (the STORE operation) takes place
automatically at power down. On power up, data is restored to
the SRAM (the RECALL operation) from the nonvolatile
memory. Both the STORE and RECALL operations are also
available under software control.
Logic Block Diagram
STORE/
RECALL
CONTROL
POWER
CONTROL
SOFTWARE
DETECT
STATIC RAM
ARRAY
1024 X 1024
QuantumTrap
1024 x 1024
STORE
RECALL
COLUMN IO
COLUMN DEC
R
I
OE
CE
WE
HSB
V
CC
V
CAP
A
15
-
A
0
A
0
A
1
A
2
A
3
A
4
A
10
A
11
A
5
A
6
A
7
A
8
A
9
A
12
A
13
A
14
A
15
A
16
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
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