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參數(shù)資料
| 型號： | CY143 |
| 英文描述： | 2K x 16 Dual-Port Static RAM(193.25 k) |
| 中文描述： | 2K × 16雙口靜態(tài)存儲器（193.25十一） |
| 文件頁數(shù)： | 1/14頁 |
| 文件大?。?/td> | 193K |
| 代理商： | CY143 |
2K x 16 Dual-Port Static RAM
CY7C133
CY7C143
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
October 14, 1999
Features
True dual-ported memory cells which allow
simultaneous reads of the same memory location
2K x 16 organization
0.65-micron CMOS for optimum speed/power
High-speed access: 25/35/55 ns
Low operating power: I
CC
= 150 mA (typ.)
Fully asynchronous operation
Master CY7C133 expands data bus width to 32 bits or
more using slave CY7C143
BUSY input flag on CY7C133; BUSY output flag on
CY7C143
Available in 68-pin PLCC
Pin-compatible and functionally equivalent to IDT7133
and IDT7143
Functional Description
The CY7C133 and CY7C143 are high-speed CMOS 2K by 16
dual-port static RAMs. Two ports are provided permitting inde-
pendent access to any location in memory. The CY7C133 can
be utilized as either a stand-alone 16-bit dual-port static RAM
or as a master dual-port RAM in conjunction with the CY7C143
slave dual-port device in systems requiring 32-bit or greater
word widths. It is the solution to applications requiring shared
or buffered data, such as cache memory for DSP, bit-slice, or
multiprocessor designs.
Each port has independent control pins; Chip Enable (CE),
Write Enable (R/W
UB
, R/W
LB
), and Output Enable (OE). BUSY
signals that the port is trying to access the same location cur-
rently being accessed by the other port. An automatic pow-
er-down feature is controlled independently on each port by
the Chip Enable (CE) pin.
The CY7C133 and CY7C143 are available in 68-pin PLCC.
Note:
1.
CY7C133 (Master): BUSY is open drain output and requires pull-up resistor. CY7C143 (Slave): BUSY is input.
C133-1
R/W
LUB
CE
L
OE
L
A
10L
A
0L
R/W
RUB
CE
R
CE
R
OE
R
R/W
RUB
R/W
RLB
CE
L
OE
L
R/W
LUB
R/W
LLB
I/O
8L
– I/O
15L
ARBITRATION
LOGIC
(CY7C133ONLY)
CONTROL
I/O
MEMORY
ARRAY
ADDRESS
DECODER
ADDRESS
DECODER
BUSY
L[1]
CONTROL
I/O
I/O
0L
– I/O
7L
R/W
RLB
OE
R
A
10R
A
0R
I/O
8R
– I/O
15R
BUSY
R
[ ]
1
I/O
0R
– I/O
7R
R/W
LLB
Logic Block Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY1E494-10DC | x4 SRAM |
| CY1E494-10JC | x4 SRAM |
| CY1E494-10KC | x4 SRAM |
| CY1E494-7DC | x4 SRAM |
| CY1E494-7JC | x4 SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY1461-000 | 制造商:TE Connectivity 功能描述:55PC0241-12-2/4/5/6CS2502 |
| CY14A | 功能描述:晶體 14.31818MHz Series 0C +70C RoHS:否 制造商:AVX 頻率:26 MHz 容差: 頻率穩(wěn)定性:50 PPM 負(fù)載電容:8 pF 端接類型:SMD/SMT 封裝 / 箱體:1210 (3225 metric) 工作溫度范圍:- 40 C to + 150 C 尺寸:2.5 mm W x 3.2 mm L x 0.85 mm H 封裝:Reel |
| CY14AC | 功能描述:晶體 14.31818MHz 18pF 0C +70C RoHS:否 制造商:AVX 頻率:26 MHz 容差: 頻率穩(wěn)定性:50 PPM 負(fù)載電容:8 pF 端接類型:SMD/SMT 封裝 / 箱體:1210 (3225 metric) 工作溫度范圍:- 40 C to + 150 C 尺寸:2.5 mm W x 3.2 mm L x 0.85 mm H 封裝:Reel |
| CY14ACS | 功能描述:晶體 14.31818MHz 18pF 0C +70C RoHS:否 制造商:AVX 頻率:26 MHz 容差: 頻率穩(wěn)定性:50 PPM 負(fù)載電容:8 pF 端接類型:SMD/SMT 封裝 / 箱體:1210 (3225 metric) 工作溫度范圍:- 40 C to + 150 C 尺寸:2.5 mm W x 3.2 mm L x 0.85 mm H 封裝:Reel |
| CY14ACSMD | 功能描述:晶體 14.31818MHz 18pF 0C +70C RoHS:否 制造商:AVX 頻率:26 MHz 容差: 頻率穩(wěn)定性:50 PPM 負(fù)載電容:8 pF 端接類型:SMD/SMT 封裝 / 箱體:1210 (3225 metric) 工作溫度范圍:- 40 C to + 150 C 尺寸:2.5 mm W x 3.2 mm L x 0.85 mm H 封裝:Reel |
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