參數(shù)資料
型號: CXP913P048
廠商: Sony Corporation
英文描述: CMOS 16-bit Single Chip Microcomputer
中文描述: 的CMOS 16位單片機
文件頁數(shù): 22/26頁
文件大小: 308K
代理商: CXP913P048
– 22 –
CXP913P048
V
DD
= 5.0V ± 10%
V
DD
= 3.0V ± 10%
V
DD
= 5.0V ± 10%
V
DD
= 3.0V ± 10%
V
DD
= 5.0V ± 10%
V
DD
= 3.0V ± 10%
V
DD
= 5.0V ± 10%
V
DD
= 3.0V ± 10%
V
DD
= 5.0V ± 10%
V
DD
= 3.0V ± 10%
V
DD
= 5.0V ± 10%
V
DD
= 3.0V ± 10%
V
DD
= 5.0V ± 10%
V
DD
= 3.0V ± 10%
V
DD
= 5.0V ± 10%
V
DD
= 3.0V ± 10%
V
DD
= 5.0V ± 10%
V
DD
= 3.0V ± 10%
V
DD
= 5.0V ± 10%
V
DD
= 3.0V ± 10%
V
DD
= 5.0V ± 10%
V
DD
= 3.0V ± 10%
(6) Other
(Ta = –20 to +75°C, V
SS
= 0V reference)
Item
t
CFH
,
t
CFL
t
DFH
,
t
DFL
t
DPW
t
DPR
t
RFH
,
t
RFL
t
EIH
,
t
EIL
t
PIH
,
t
PIL
t
PMW
t
PMR
t
TLH
t
THL
CFG
DFG
DPG
DPG
RFG0
RFG1
EXI0
EXI1
PMI
PMSK
PMSK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Symbol
Pin
Min.
50
100
20
40
Typ.
100
280
40
80
Max.
Unit
Conditions
t
sys +200
t
sys +200
1000/fc +200
1000/fc +200
50
50
50
50
t
sys +200
t
sys +200
t
sys +200
t
sys +200
t
sys +200
t
sys +200
t
sys +200
t
sys +200
t
sys +200
t
sys +200
Note)
t
sys indicates the three values below according to the upper two bits (CPU clock selected) of the clock
control register (CLC: 0002FEh).
t
sys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits =
"11")
CFG input high,
low level width
DFG input high,
low level width
DPG minimum
pulse width
DPG minimum
removal time
RFG input high,
low level width
EXI input high,
low level width
PMI input high,
low level width
PMSK minimum
pulse width
PMSK minimum
removal time
XOUT output rise
time, fall time
When the
load is
50pF
When
t
sys
= 2000/fc
XOUT
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