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參數(shù)資料
| 型號(hào)： | CXP85856AS |
| 廠商： | Sony Corporation |
| 英文描述： | MICROCONTROLLER|8-BIT|SPC700 CPU|CMOS|SDIP|64PIN|PLASTIC |
| 中文描述： | 單片機(jī)| 8位| SPC700 CPU的|的CMOS | SDIP接插| 64管腳|塑料 |
| 文件頁數(shù)： | 17/22頁 |
| 文件大小： | 277K |
| 代理商： | CXP85856AS |
– 17 –
CXP85840A/85848A/85856A
(6) I
2
C bus timing
(Ta = –20 to +75°C, V
DD
= 4.5 to 5.5V, Vss = 0V reference)
Item
SCL clock frequency
Bus-free time before starting transfer
Hold time for starting transfer
Clock Low level width
Clock High level width
Setup time for repeated transfers
Data hold time
Data setup time
SDA, SCL rise time
SDA, SCL fall time
Setup time for transfer completion
1
The data hold time should be 300ns or more because the SCL rise time (300ns Max.) is not included in it.
f
SLC
t
BUF
t
HD; STA
t
LOW
t
HIGH
t
SU; STA
t
HD; DAT
t
SU; DAT
t
R
t
F
t
SU; STO
SCL
SDA, SCL
SDA, SCL
SCL
SCL
SDA, SCL
SDA, SCL
SDA, SCL
SDA, SCL
SDA, SCL
SDA, SCL
0
4.7
4.0
4.7
4.0
4.7
0
1
250
4.7
100
1
300
kHz
μs
μs
μs
μs
μs
μs
ns
μs
ns
μs
Symbol
Pins
Conditions
Min.
Max.
Unit
Fig. 9. I
2
C bus transfer timing
P
St
t
SU; STO
t
SU; STA
t
HD; STA
t
SU; DAT
t
HIGH
t
HD; DAT
t
F
t
R
t
LOW
t
HD; STA
S
P
t
BUF
SDA
SCL
Fig. 10. I
2
C bus device recommended circuit
I
2
C
device
I
2
C
device
R
S
R
S
R
S
R
S
R
P
R
P
SDA0
(or SDA1)
SCL0
(or SCL1)
A pull-up resistor (Rp) must be connected to SDA0 (or SDA1) and SCL0 (or SCL1).
The SDA0 (or SDA1) and SCL0 (or SCL1) series resistance (Rs = 300
or less) can be used to reduce the
spike noise caused by CRT flashover.
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