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– 21 –
CXP84632/84640/84648
Serial transfer (CH1, CH2)
(Ta = –20 to +75°C, V
DD
= 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
Pin
Min.
Max.
Unit
Condition
SCK cycle time
SCK High and Low
level widths
SI input setup time
(against SCK
↑
)
SI input hold time
(against SCK
↑
)
SCK
↓ →
SO delay time
t
KCY
t
KH
t
KL
t
SIK
t
KSI
t
KSO
SCK1
SCK2
SCK1
SCK2
SI1
SI2
SI1
SI2
SO1
SO2
Input mode
Output mode
Input mode
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
2
t
sys + 200
16000/fc
t
sys + 100
8000/fc – 50
100
200
t
sys + 200
100
t
sys + 200
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1)
t
sys indicates three values according to the contents of the clock control register (CLC; 00FE
H
) upper
2 bits (CPU clock selection).
t
sys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01’), 16000/fc (Upper 2 bits = “11”)
Note 2)
SCK, SI and SO represent SCK1, SI1, and SO1, respectively for CH1; they represent SCK2, SI2 and
SO2, respectively for CH2.
Note 3)
The load of SCK1 and SCK2 output modes and SO1 and SO2 output delay times is 50pF+1TTL.
Serial transfer (CH1, CH2)
(Ta = –20 to +75°C, V
DD
= 3.0 to 3.6V, Vss = 0V reference)
Item
Symbol
Pin
Min.
Max.
Unit
Condition
SCK cycle time
SCK High and Low
level widths
SI input setup time
(against SCK
↑
)
SI input hold time
(against SCK
↑
)
SCK
↓ →
SO delay time
t
KCY
t
KH
t
KL
t
SIK
t
KSI
t
KSO
SCK1
SCK2
SCK1
SCK2
SI1
SI2
SI1
SI2
SO1
SO2
Input mode
Output mode
Input mode
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
2
t
sys + 200
16000/fc
t
sys + 100
8000/fc – 150
100
200
t
sys + 200
100
t
sys + 250
125
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1)
t
sys indicates three values according to the contents of the clock control register (CLC; 00FE
H
) upper
2 bits (CPU clock selection).
t
sys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01’), 16000/fc (Upper 2 bits = “11”)
Note 2)
SCK, SI and SO represent SCK1, SI1, and SO1, respectively for CH1; they represent SCK2, SI2 and
SO2, respectively for CH2.
Note 3)
The load of SCK1 and SCK2 output modes and SO1 and SO2 output delay times is 50pF.