參數(shù)資料
型號(hào)： CXP83625Q
廠商： Sony Corporation
英文描述： Microcontroller
中文描述： 微控制器
文件頁(yè)數(shù)： 21/30頁(yè)
文件大小： 423K
代理商： CXP83625Q
– 21 –
CXP83620/83624, CXP83621/83625
Chip select transfer mode
(SCK = output mode)
Chip select transfer mode
(SCK = output mode)
Chip select transfer mode
Chip select transfer mode
Chip select transfer mode
Note 1)
t
sys indicates the three values below according to the upper two bits (CPU clock selection) of the
clock control register (CLC: 00FEh).
t
sys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”)
Note 2)
CS, SCK, SI and SO indicates CS0, SCK0, SI0 and SO0, respectively.
Note 3)
The load condition for the SCK output mode, SO output delay time is 50pF.
Note 4)
The value when Port B output buffer capability switching register (BUFB: 01F4h) selects buffer
capability to high.
Serial transfer (CH0)
(Ta = –20 to +75°C, V
DD
= 2.7 to 3.3V, Vss = 0V)
Item
CS
↓ →
SCK
delay time
CS
↑ →
SCK
float delay time
CS
↓ →
SO
delay time
CS
↓ →
SO
float delay time
CS high level width
SCK cycle time
SCK high and low
level widths
SI input setup time
(for SCK
↑
)
SI input hold time
(for SCK
↑
)
SCK
↓ →
SO
delay time
t
DCSK
t
DCSKF
t
DCSO
t
DCSOF
t
WHCS
t
KCY
t
KH
t
KL
t
SIK
t
KSI
t
KSO
SCK0
SCK0
SO0
SO0
CS0
SCK0
SCK0
SI0
SI0
SO0
Input mode
Output mode
Input mode
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
ns
ns
ns
ns
ns
Symbol
Pin
Min.
t
sys + 250
t
sys + 200
t
sys + 250
t
sys + 200
t
sys + 200
2
t
sys + 200
16000/fc
t
sys + 100
8000/fc – 150
–
t
sys + 100
200
2
t
sys + 100
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
t
sys + 250
125
Max.
Unit
Conditions
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