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– 19 –
CXP81120/81124
Serial transfer (CH1) (SIO mode)
(Ta = –20 to +75°C, V
DD
= 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
Pin
Min.
Max.
Unit
Condition
SCK1 cycle time
SCK1 high and low
level widths
SI1 input setup time
(for SCK1
↑
)
SI1 input hold time
(for SCK1
↑
)
SCK1
↓ →
SO1 delay time
t
KCY
t
KH
t
KL
t
SIK
t
KSI
t
KSO
SCK1
SCK1
SI1
SI1
SO1
Input mode
Output mode
Input mode
Output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode
2
t
sys + 200
16000/fc
t
sys + 100
8000/fc – 50
100
200
t
sys + 200
100
t
sys + 200
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1)
t
sys indicates three values according to the contents of the clock control register (CLC; 00FE
H
) upper
2 bits (CPU clock selection).
t
sys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”)
Note 2)
The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL.
Serial transfer (CH1) (SIO mode)
(Ta = –20 to +75°C, V
DD
= 3.0 to 3.6V, Vss = 0V reference)
Item
Symbol
Pin
Min.
Max.
Unit
Condition
SCK1 cycle time
SCK1 high and low
level widths
SI1 input setup time
(for SCK1
↑
)
SI1 input hold time
(for SCK1
↑
)
SCK1
↓ →
SO1 delay time
t
KCY
t
KH
t
KL
t
SIK
t
KSI
t
KSO
SCK1
SCK1
SI1
SI1
SO1
Input mode
Output mode
Input mode
Output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode
2
t
sys + 200
16000/fc
t
sys + 100
8000/fc – 150
100
200
t
sys + 200
100
t
sys + 250
125
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1)
t
sys indicates three values according to the contents of the clock control register (CLC; 00FE
H
) upper
2 bits (CPU clock selection).
t
sys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”)
Note 2)
The load of SCK1 output mode and SO1 output delay time is 50pF.