
CMOS-CCD 1H Delay Line for NTSC
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Description
The CXL5504M/P are CMOS-CCD delay line ICs
that provide 1H delay time for NTSC signals including
the external low-pass filter.
Features
Single power supply (5V)
Low power consumption 90mW (Typ.)
Built-in peripheral circuits
Clamp level of I/O signal can be selected
Functions
905-bit CCD register
Clock driver
Autobias circuit
Input clamp circuit
Sample and hold circuit
Structure
CMOS-CCD
Absolute Maximum Ratings
(Ta = 25°C)
Supply voltage
Operating temperature Topr
Storage temperature
Allowable power dissipation
V
DD
6
V
–10 to +60
–55 to +150
°C
°C
Tstg
P
D
CXL5504M
CXL5504P
350
480
mW
mW
Recommended Operating Condition
(Ta = 25°C)
Supply voltage
V
DD
5 ± 5%
V
Recommended Clock Conditions
(Ta = 25°C)
Input clock amplitude
V
CLK
0.4 to 1.0
(0.5Vp-p typ.)
14.318182
Sine wave
Vp-p
Clock frequency
Input clock waveform
f
CLK
MHz
Input Signal Amplitude
V
SIG
500mVp-p (Typ.), 572mVp-p (Max.)
(at internal clamp condition)
– 1 –
E89931C79-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CXL5504M/P
CXL5504M
8 pin SOP (Plastic)
CXL5504P
8 pin DIP (Plastic)
Blook Diagram and Pin Configration
(Top View)
Output circuit
(S/H 1bit)
C
1
I
2
3
4
5
7
8
Autobias circuit
Timing circuit
Bias circuit
CCD
(905bit)
Clock driver
Bias circuit (A)
Bias circuit (B)
I/O control
Clamp circuit
6
I
V
D
A
V
S
O
I