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參數(shù)資料
| 型號(hào)： | CXL1506M |
| 廠商： | Sony Corporation |
| 英文描述： | CMOS-CCD 1H/2H Delay Line for PAL |
| 中文描述： | CMOS與CCD 1H/2H延遲線對(duì)于PAL |
| 文件頁(yè)數(shù)： | 1/12頁(yè) |
| 文件大?。?/td> | 170K |
| 代理商： | CXL1506M |
CMOS-CCD 1H/2H Delay Line for PAL
For the availability of this product, please contact the sales office.
Description
The CXL1506M/N is a CMOS-CCD delay line
developed for video signal processing. Usage in
conjunction with an external low pass filter provides
1H and 2H delay signals simultaneously (For PAL
signals).
Features
Single power supply (5V)
Low power consumption
Built-in peripheral circuits
Built-in tripling PLL circuit
For PAL signals
1 input and 2 outputs
(Outputs for both 1H and 2H delays)
Absolute Maximum Ratings
(Ta = 25°C)
Supply voltage
Operating temperature
Storage temperature
Allowable power dissipation
V
DD
Topr
Tstg
6
V
–10 to +60
–55 to +150
°C
°C
P
D
CXL1506M 400 mW
CXL1506N 300 mW
Recommended Operating Voltage
(Ta = 25°C)
V
DD
5 ± 0.25
V
Recommended Clock Conditions
(Ta = 25°C)
Input clock amplitude
Input clock frequency
Input clock waveform
V
CLK
0.2 to 1.0Vp-p (0.4Vp-p Typ.)
f
CLK
4.433619
sine wave
MHz
Input Signal Amplitude
V
SIG
575 (Max.) mVp-p (at internal clamp condition)
– 1 –
E89X22C78-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CXL1506M/N
CXL1506M
16 pin SOP (Plastic)
CXL1506N
20 pin SSOP (Plastic)
Blook Diagram
CXL1506N
CXL1506M
Autobias circuit
Driver
Bias
circuit
PLL
Timing
CCD (1698bits)
Clamp circuit
Output circuit
S/H 1bit
AA
AA
12
13
10
11
2
5
6
7
1
IN
V
SS
V
DD
VIN
PC
OUT
V
SS
VG1
VG2
OUT1
(1H)
V
SS
OUT2
(2H)
8
CLK
V
SS
(VCO OUT)
15
16
AB
V
DD
V
SS
Output circuit
S/H 1bit
9
4
847bits
1698bits
3
Autobias circuit
Driver
Bias
PLL
Timing
CCD (1698bits)
Clamp circuit
Output circuit
S/H 1bit
AA
AA
12
13
10
V
SS
11
2
IN
5
6
7
1
V
SS
NC
V
DD
VCO
IN
PC
V
SS
VG1
VG2
OUT1
(1H)
V
SS
OUT2
(2H)
8
CLK
V
SS
(VCO OUT)
NC
15
16
17
18
19
20
AB
V
DD
NC
NC
Output circuit
S/H 1bit
9
4
847bits
1698bits
3
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PDF描述 |
|---|---|
| CXL1506N | CMOS-CCD 1H/2H Delay Line for PAL |
| CXL1517 | CMOS-CCD Signal Processor |
| CXL1517M | CMOS-CCD Signal Processor |
| CXL1517N | CMOS-CCD Signal Processor |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CXL1506M/N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS-CCD 1H/2H Delay Line for PAL |
| CXL1506N | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CMOS-CCD 1H/2H Delay Line for PAL |
| CXL1510M | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CCD Delay Line for Multi System |
| CXL1511M | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CCD Delay Line for PAL |
| CXL1512M | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CCD Delay Line for NTSC |
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