參數(shù)資料
型號： CXK79M36C160GB-33
元件分類： SRAM
英文描述： 512K X 36 STANDARD SRAM, 1.8 ns, PBGA209
封裝： 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-209
文件頁數(shù)： 1/28頁
文件大?。?/td> 493K
代理商： CXK79M36C160GB-33
18Mb 1x1Lp, HSTL, rev 1.1
1 / 28
November 8, 2002
CXK79M72C160GB / CXK79M36C160GB
SONY
ΣRAM
33/4/5
18Mb 1x1Lp HSTL High Speed Synchronous SRAMs (256Kb x 72 or 512Kb x 36)
Preliminary
Description
The CXK79M72C160GB (organized as 262,144 words by 72 bits) and the CXK79M36C160GB (organized as 524,288 words
by 36 bits) are high speed CMOS synchronous static RAMs with common I/O pins. They are manufactured in compliance with
the JEDEC-standard 209 pin BGA package pinouts defined for SigmaRAM devices. They integrate input registers, high speed
RAM, output registers, and a two-deep write buffer onto a single monolithic IC. Single Data Rate (SDR) Pipelined (PL) read
operations and Late Write (LW) write operations are supported, providing a high-performance user interface. Positive and neg-
ative output clocks are provided for applications requiring source-synchronous operation.
All address and control input signals are registered on the rising edge of the CK differential input clock.
During read operations, output data is driven valid once, from the rising edge of CK, one full cycle after the address and control
signals are registered.
During write operations, input data is registered once, on the rising edge of CK, one full cycle after the address and control
signals are registered.
Output drivers are series-terminated, and output impedance is programmable via the ZQ control pin. When an external resistor
RQ is connected between ZQ and VSS, the impedance of the SRAM’s output drivers is set to ~RQ/5.
300 MHz operation (300 Mbps) is obtained from a single 1.8V power supply. JTAG boundary scan interface is provided using
a subset of IEEE standard 1149.1 protocol.
Features
3 Speed Bins
CycleTime/Data Access Time
-33
3.3ns / 1.8ns
-4
4.0ns / 2.1ns
-5
5.0ns / 2.3ns
Single 1.8V power supply (VDD): 1.7V (min) to 1.95V (max)
Dedicated output supply voltage (VDDQ): 1.4V (min) to VDD (max)
HSTL-compatible I/O interface with dedicated input reference voltage (VREF): VDDQ/2 typical
Common I/O
Single Data Rate (SDR) data transfers
Pipelined (PL) read operations
Late Write (LW) write operations
Burst capability with internally controlled Linear Burst address sequencing
Burst length of two, three, or four, with automatic address wrap
Full read/write data coherency
Byte write capability
Differential input clocks (CK and CK)
Data-referenced output clocks (CQ1, CQ1, CQ2, CQ2)
Programmable output driver impedance via dedicated control pin (ZQ)
Depth expansion capability (2 or 4 banks) via programmable chip enables (E2, E3, EP2, EP3)
JTAG boundary scan (subset of IEEE standard 1149.1)
209 pin (11x19), 1mm pitch, 14mm x 22mm Ball Grid Array (BGA) package
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CXK79M36C161GB 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEMORY-SigmaRAM 16Meg 1x1 LVCMOS I/O (512K x 36) (27 pages 364K Rev. 7/6/01)
CXK79M36C162GB 制造商:SONY 制造商全稱:Sony Corporation 功能描述:18Mb 1x2Lp HSTL High Speed Synchronous SRAMs (512Kb x 36)
CXK79M36C162GB-33 制造商:SONY 制造商全稱:Sony Corporation 功能描述:18Mb 1x2Lp HSTL High Speed Synchronous SRAMs (512Kb x 36)
CXK79M36C162GB-4 制造商:SONY 制造商全稱:Sony Corporation 功能描述:18Mb 1x2Lp HSTL High Speed Synchronous SRAMs (512Kb x 36)
CXK79M36C162GB-5 制造商:SONY 制造商全稱:Sony Corporation 功能描述:18Mb 1x2Lp HSTL High Speed Synchronous SRAMs (512Kb x 36)
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