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參數(shù)資料
| 型號(hào)： | CXK77920YM |
| 廠商： | Sony Corporation |
| 英文描述： | 262144-Word x 9-Bit High Speed Synchronous Static RAM(262144字 × 9位高速同步靜態(tài)RAM) |
| 中文描述： | 262144字× 9位高速同步靜態(tài)存儲(chǔ)器（262144字× 9位高速同步靜態(tài)內(nèi)存） |
| 文件頁(yè)數(shù)： | 1/12頁(yè) |
| 文件大小： | 122K |
| 代理商： | CXK77920YM |
CXK77920TM/YM-
11/12/15
262144-word x 9-bit High Speed Synchronous Static RAM
Description
The CXK77920TM/YM is a high speed CMOS
synchronous static RAM with common l/O pins, orga-
nized as 262144-word-by-9-bit. This synchronous SRAM
integrates input registers, high speed SRAM and output
registers onto a single monolithic IC. All input signals are
latched at the positive edge of an external clock (CLK).
The RAM data from the previous cycle is presented at
the positive edge of the subsequent clock cycle. Write
operation is initiated by the positive edge of CLK and is
internally self-timed. This feature eliminates complex
off-chip write pulse generation and provides increased
flexibility for incoming signals. 90MHz operation is
obtained from a single 5V power supply.
Function
There are three possible user transactions with the
STRAM: Read operation, write operation and deselect
operation.
The read operation requires
WE
= “HIGH” and
OE
=
CE
= “LOW” on the positive edge of CLK.
The memory location pointed to by the contents of the
Address registers is read internally and the contents
of the location are captured in the Data-out registers
on the next positive edge of CLK. The state of
Data-out will reflect the contents of the Data-out regis-
ters.
The write operation requires
CE
=
WE
= “LOW” on the
positive edge of CLK. The memory location pointed to
by the contents of the Address registers is written with
the contents of the Data-in registers. The write opera-
tion is entirely self-timed, eliminating critical timing
edges.
The deselect cycle requires
CE
= “HIGH” or
OE
=
WE
= “HIGH” on the positive edge of CLK. Write operation
and internal read operation are disabled during the
clock cycle. The data outputs are forced to a high
impedance state during the next clock cycle. During
the deselect cycle by
CE
= “HIGH”, STRAM turns to
power down mode.
–1–
E93Z08-ST
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication
or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony
cannot assume responsibility for any problems arising out of the use of these circuits.
Structure
Silicon gate CMOS IC
Features
Fast cycle time:
CXK77920TM/YM-11
CXK77920TM/YM-12
CXK77920TM/YM-15
Fast clock to data valid
CXK77920TM/YM-11
CXK77920TM/YM-12
CXK77920TM/YM-15
High speed, low power consumption
Single +5V power supply: 5V±5%
Separate output power supply: 3.15 to 5.25V
Inputs and outputs are TTL compatible
(3.3V l/O compatible)
Common data input and output
All inputs and outputs are registered on a single clock
edge
Self-timed write cycle
Package line-up:
400mil, 44 pin TSOP II with 0.8mm pitch
(Cycle)
11.0ns
12.5ns
15.0ns
(Frequency)
90MHz
80MHz
66.7MHz
6.0ns
6.5ns
7.0ns
CXK77920TM
44pin TSOP (II)
(Plastic)
CXK77920YM
44pin TSOP (II)
(Plastic)
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| CXK77920YM-12 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Synchronous SRAM |
| CXK77920YM-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Synchronous SRAM |
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| CXK77B1810-7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous SRAM |
| CXK77B1810AGB | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:High Speed Bi-CMOS Synchronous Static RAM |
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