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參數(shù)資料
| 型號： | CXD8302Q |
| 廠商： | Sony Corporation |
| 英文描述： | PLL For CCD Cameras(用于CCD照相機的鎖相環(huán)電路) |
| 中文描述： | CCD相機的PLL（用于防治荒漠化公約照相機的鎖相環(huán)電路） |
| 文件頁數(shù)： | 3/10頁 |
| 文件大小： | 183K |
| 代理商： | CXD8302Q |
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CXD8302Q
Pin Description
Pin No.
Symbol
I/O
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
V
SS
DLY0
DLY1
DLY2
V
DD
V
SS
DLY3
DLY4
DLY5
DLY6
DLY7
V
SS
EXTVD
EXTHD
EXTSYNC
V
SS
V
DD
TEST1
EXTf
H
INTf
H
TEST2
TEST3
V
SS
NC
TEST4
MODE
TEST5
V
SS
V
DD
TEST6
MODE2
EIA/CCIR
NC
V
SS
TEST7
NC
CLKO
—
I
I
I
—
—
I
I
I
I
I
—
I
I
I
—
—
O
O
O
O
O
—
—
I
I
I
—
—
I
I
I
—
—
O
—
O
Pin 20 (INTf
H
) phase setting.
(With pull-up resistor)
Pin 20 (INTf
H
) phase setting.
(With pull-up resistor)
Pin 20 (INTf
H
) phase setting.
(With pull-up resistor)
Pin 20 (INTf
H
) phase setting.
(With pull-up resistor)
Pin 20 (INTf
H
) phase setting.
(With pull-up resistor)
Pin 20 (INTf
H
) phase setting.
(With pull-up resistor)
Pin 20 (INTf
H
) phase setting.
(With pull-up resistor)
Pin 20 (INTf
H
) phase setting (MSB).
(With pull-up resistor)
External VD input.
(With pull-up resistor)
External HD input.
(With pull-up resistor)
External SYNC input.
(With pull-up resistor)
Test output (normally OPEN).
External f
H
output.
Internal f
H
output.
Test output (normally OPEN).
Test output (normally OPEN).
Test input (normally High).
(With pull-up resistor)
High: SYNC sync mode, Low: VD/HD sync mode.
(With pull-up resistor)
Test input (normally Low).
(With pull-down resistor)
Test input (normally High).
(With pull-up resistor)
High: Component digital mode, Low: Composite digital mode.
(With pull-up resistor)
High: EIA mode, Low: CCIR mode.
(With pull-up resistor)
Test output (normally OPEN).
Inversed output of CLKI.
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