參數(shù)資料
型號(hào): CXD3611R
廠商: Sony Corporation
英文描述: Timing Generator for Progressive Scan CCD Image Sensor
中文描述: 時(shí)序發(fā)生器傳感器逐行掃描CCD圖像
文件頁(yè)數(shù): 4/49頁(yè)
文件大?。?/td> 429K
代理商: CXD3611R
4
CXD3611R
Pin Description
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Symbol
V
SS
1
SNCSL
SSGSL
CCD
MD1
MD2
MD3
SMD1
SMD2
SMD3
HDRS
CDSRS
V
DD
1
RG
V
SS
2
H1
H2
V
DD
2
V
DD
3
XSHP
XSHD
XRS
PBLK
CLPDM
OBCLP
ADCLK
V
SS
3
I/O
I
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
O
O
O
O
O
Description
GND
Control input used to switch sync system
High: CKI sync, Low: MCKO sync.
With pull-down resistor
Pin used to switch external reset
High: External sync has priority, Low: Internal sync has priority
With pull-down resistor
Control input used to switch CCD
High: ICX415, Low: ICX414/424
With pull-down resistor
Control input 1 used to switch drive mode
See the section on parallel control
With pull-down resistor
Control input 2 used to switch drive mode
See the section on parallel control
With pull-down resistor
Control input 3 used to switch drive mode
See the section on parallel control
With pull-down resistor
Control input 1 used to switch exposure time
See the section on parallel control
With pull-down resistor
Control input 2 used to switch exposure time
See the section on parallel control
With pull-down resistor
Control input 3 used to switch exposure time
See the section on parallel control
With pull-down resistor
Control input used to switch H system pulse polarity
H1 and H2 are targeted (Default is positive polarity.)
High: For external Dr, Low: For internal Dr
With pull-down resistor
Control input used to switch CDS system pulse polarity
XSHP XSHD, XRS, OBCLP CLPDM are targeted.
High: Positive polarity, Low: Negative polarity
With pull-down resistor
3.3V power supply. (Power supply for common logic block)
CCD reset gate pulse output
GND
CCD horizontal register clock output
CCD horizontal register clock output
3.3V power supply. (Power supply for H1/H2/RG)
3.3V power supply. (Power supply for CDS)
CCD precharge level sample-and-hold pulse output
CCD data level sample-and-hold pulse output
Sample-and-hold pulse output for analog/digital conversion phase alignment
Pulse output for horizontal and vertical blanking period pulse cleaning
CCD dummy signal clamp pulse output
CCD optical black signal clamp pulse output
Clock output for analog/digital conversion IC
Logical phase can be adjusted using serial interface data.
GND
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