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參數(shù)資料
| 型號(hào)： | CXD3511 |
| 廠商： | Sony Corporation |
| 英文描述： | Digital Signal Driver/Timing Generator |
| 中文描述： | 數(shù)字信號(hào)驅(qū)動(dòng)器/時(shí)序發(fā)生器 |
| 文件頁數(shù)： | 15/84頁 |
| 文件大?。?/td> | 569K |
| 代理商： | CXD3511 |
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15
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CXD3511AQ
Description of Operation
1. Description of Input Pins
(a) System clear pins (XCLR1, XCLR2 and XCLR3)
All internal circuits are initialized by setting XCLR1 (Pin 27) low. In addition, the internal PLL is initialized by
setting XCLR2 (Pin 28) low, and RGB output is initialized (preset) by setting XCLR3 (Pin 29) low.
Initialization should be performed when power is turned on. There are no particular restrictions on the
initialization order.
(b) Sync signal input pins (HDIN and VDIN)
Horizontal and vertical separate sync signals are input to HDIN (Pin 31) and VDIN (Pin 32), respectively. The
CXD3511AQ supports only non-interlace sync signals with a dot clock of 200MHz or less.
(c) Master clock input pins (CLKP/CLKN and CLKC)
Phase comparison is performed by an external circuit and a clock synchronized to the sync signal is input. The
master clock input pins have two systems consisting of CLKP/CLKN (Pins 38 and 39) for small-amplitude
differential input (center level: 2.0V, amplitude: ±0.4V), and CLKC (Pin 35) for CMOS level input. In addition, be
sure to make the number of dot clocks in 1H as even number.
Note that if there is an odd number of dot clocks, the internal phase compensation PLL will not operate
properly.
(d) Clock selection pins (CLKSEL1 and CLKSEL2)
The master clock input pins can input either the system dot clock or the 1/2 frequency-divided clock. The
internal clock path is selected according to CLKSEL1 (Pin 41) and CLKSEL2 (Pin 44).
(e) PLL setting pin (PLLDIV)
PLLDIV (Pin 45) sets the divider setting of the internal phase compensation PLL circuit. Set PLLDIV low when
the internal clock frequency is 55 to 100MHz, or high when 27.5 to 55MHz. In addition, note that the frequency
of the clock input to the CXD3511AQ must be within the phase compensation PLL operating range, even during
free running.
Symbol
CLKSEL1
CLKSEL2
Function
Input clock selection
Clock input pin selection
Setting
L
CLKP/CLKN input
Dot clock input
H
CLKC input
1/2 frequency-divided clock input
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CXD3511AQ | Digital Signal Driver/Timing Generator |
| CXD3519 | Reference Voltage and Driver IC for LCD |
| CXD3519TQ | Reference Voltage and Driver IC for LCD |
| CXD3521GG | Interface and Driver IC for LCD |
| CXD3526GG | Digital Signal Driver/Timing Generator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CXD3511AQ | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Digital Signal Driver/Timing Generator |
| CXD3511Q | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Digital Signal Driver/Timing Generator |
| CXD3513 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Interface and Driver IC for LCD |
| CXD3513GG | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Interface and Driver IC for LCD |
| CXD3519 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Reference Voltage and Driver IC for LCD |
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