參數(shù)資料
型號(hào): CXD3504R
廠商: Sony Corporation
英文描述: Selective Delay Line For LCD(用于LCD的可選擇延遲線)
中文描述: 選擇性延遲線在液晶(用于液晶顯示器的可選擇延遲線)
文件頁數(shù): 10/12頁
文件大?。?/td> 236K
代理商: CXD3504R
– 10 –
CXD3504R
Description of Operation
1) The following describes only R, but the operation for G and B is the same.
SELRA:SELB = 0:0
R2IN
R1IN
SELRA:SELB = 0:1
R2IN
R1IN
SELRA:SELB = 1:0
R1IN
R2IN
SELRA:SELB = 1:1
R1IN
R2IN
However, POLSLA = 0
through
delay
delay
through
through
delay
delay
through
R1OUT
R2OUT
R1OUT
R2OUT
R1OUT
R2OUT
R1OUT
R2OUT
2) Be sure to set XCLR to "0" for a clock or more while HD is "1". (when HDSEL = 0) Also, input the HD signal
with a "0" period length of 6 clocks or more.
Very Little Signal Amplifier
(V
DD
= 3.0 to 3.6V, Vss = 0V, Ta = –30 to +75°C)
Item
High level input voltage
Low level input voltage
Input frequency
Input amplitude
1
Symbol
V
IH
V
IL
f
Vpp
Min.
0.4
0
0.4
Typ.
Max.
3.6
3.2
80
Unit
V
V
MHz
V
Applicable pins: PECLCK (Pin 2)
1
Input the signal through a capacitor. Also, this amplitude is the value between the through capacitor and the
input pin.
2
PECLCK
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