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參數(shù)資料
| 型號： | CXD3500R |
| 廠商： | Sony Corporation |
| 英文描述： | Timing Generator for LCD Panel(LCD面板的定時(shí)信號發(fā)生器) |
| 中文描述： | 時(shí)序發(fā)生器的液晶面板（液晶面板的定時(shí)信號發(fā)生器） |
| 文件頁數(shù)： | 6/73頁 |
| 文件大?。?/td> | 792K |
| 代理商： | CXD3500R |
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CXD3500R
2. AC characteristics
(V
DD
= 5.0 ± 0.5V, V
SS
= 0V, Topr = –20 to +75°C)
3. Serial transfer AC characteristics
(V
DD
= 5.0 ± 0.5V, V
SS
= 0V, Topr = –20 to +75°C)
Item
Clock input cycle
CKI1
CKI2
All outputs
All outputs
HCK1, 2
HCK1
HCK2
t
r
t
f
t
t
H
/(
t
H
+
t
L
)
t
L
/(
t
H
+
t
L
)
Output rise time
Output fall time
Cross-point time difference
HCK1 Duty
HCK2 Duty
18.2
18.2
–10
48
48
20
20
10
52
52
ns
%
CL = 30pF
Applicable pins
Symbol
Conditions
Min.
Typ.
Max.
Unit
Note)
The minimum value for the clock input cycle (CKI1) when using the built-in double-speed controller is 27ns.
Item
SCTR setup time with respect to rise of SCLK
SDAT setup time with respect to rise of SCLK
SCTR hold time with respect to rise of SCLK
SDAT hold time with respect to rise of SCLK
SCLK L level pulse width
SCLK H level pulse width
4Tns
2Tns
4Tns
2Tns
2Tns
2Tns
5Tns
5Tns
Min.
Typ.
Max.
t
s0
t
s1
t
h0
t
h1
t
W
1L
t
W
1H
t
W
2
t
W
3
Symbol
T: Input clock cycle
Note)
Consider the frequency at free running (no signal). When the above characteristic specification is not
satisfied at free running, IC operation including serial transfer is not guaranteed.
4. External clock input AC characteristics
(V
DD
= 5.0 ± 0.5V, V
SS
= 0V, Topr = –20 to +75°C)
Item
HSYNC setup time with respect to rise of CKI1
HSYNC hold time with respect to rise of CKI1
HSYNC setup time with respect to rise of CKI2
HSYNC hold time with respect to rise of CKI2
CKI1,2 L/H level pulse width
HSYNC setup time with respect to rise of CKI1
HSYNC hold time with respect to rise of CKI1
HSYNC setup time with respect to rise of CKI2
HSYNC hold time with respect to rise of CKI2
CKI1,2 L/H level pulse width
4
7
2
9
6
0
6
0
8
40
60
Min.
T/2
50
Typ.
Max. Unit
t
s0
t
h0
t
s0
t
h0
t
W
L/
t
W
H
t
s0
t
h0
t
s0
t
h0
t
W
L/
t
W
H
Symbol
SLCK
1
: H
CKPOL
2
: H
SLRS
3
: L
SLCK
1
: L
CKPOL
2
: H
Conditions
1
,
2
,
3
: Serial data Add. 0A
T: Input clock cycle
Note)
During external clock input, set serial data HR to L. The pulse synchronized to the horizontal sync signal is
generated by detecting the front edge of the horizontal sync signal and then resetting the internal PLL counter.
ns
%
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| CXD3503R | Color Shading Correction IC for Liquid Crystal Projectors |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CXD3503R | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Color Shading Correction IC for Liquid Crystal Projectors |
| CXD3504R | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Color Shading Correction IC for Liquid Crystal Projectors |
| CXD3508ATQ | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:LCD Interface IC |
| CXD3508BTQ | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:LCD Interface IC |
| CXD3508TQ | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:LCD Interface IC |
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