參數(shù)資料
型號(hào)： CXD3406GA
廠商： Sony Corporation
英文描述： Silver Mica Capacitor; Capacitance:30000pF; Capacitance Tolerance:+/- 2%; Series:CD42; Voltage Rating:500VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:27mm; Leaded Process Compatible:Yes RoHS Compliant: Yes
中文描述： 時(shí)序發(fā)生器和幀讀出CCD圖像傳感器信號(hào)處理器
文件頁(yè)數(shù)： 24/46頁(yè)
文件大?。?/td> 384K
代理商： CXD3406GA
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CXD3406GA
The frame shift data is expressed as shown in the table below using D16 to D23 CDAT.
MSB
LSB
D23
D22
D21
D20
D19
D18
D17
D16
0
1
1
0
↓
6
1
0
0
1
↓
9
CDAT is expressed as 69h .
Its definition area is specified as follows.
AF1 mode: 00h
≤
CDAT
≤
FFh (11 to 23H)
AF2 mode: 00h
≤
CDAT
≤
FFh (14 to 27H)
Control data: [AF drive]
The CXD3406GA controls the drive of the vertical cut-out area of the line in AF1/AF2 mode by using control
data D16 to D23 CDAT. This mode has a function on purpose to raise frame rate for auto focus (AF), and
cannot support operation such as electrical image stabilization.
The AF drive bits are loaded to the CXD3406GA and reflected at the falling edge of VD. As shown in the figure
below, first, the fixed stage is swept at high speed, and it goes to readout period and vertical OB period. Then
normal transfer is performed equivalent to draft mode from the frame shift to the stage specified by the serial
interface data to the timing of the falling edge of the next VD.
Therefore, the number of frame shift stages applied to CDAT and the control by VD period are conditions for
its application.
VD
0
V1A
Vck
MODE
00h
FFh
CDAT
4
0
00h
Frame shift
Normal transfer
High-speed sweep
The number of high-speed sweep are different according to the selected mode. They are specified as follows.
AF1 mode: 138 stages (0 to 7H)
AF2 mode: 208 stages (0 to 11H)
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