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參數(shù)資料
| 型號(hào)： | CXD2598 |
| 廠商： | Sony Corporation |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理 |
| 英文描述： | CD Digital Signal Processor with Built-in Digital Servo and DAC |
| 中文描述： | CD數(shù)字信號(hào)處理器，具有內(nèi)置數(shù)字伺服和DAC |
| 文件頁(yè)數(shù)： | 113/147頁(yè) |
| 文件大小： | 1124K |
| 代理商： | CXD2598 |
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CXD2598Q
§5-13. COUT Signal
The COUT signal is output to count the number of tracks during traverse, etc. It is basically generated by
loading the MIRR signal at both edges of the TZC signal. The used TZC signal can be selected from among
three different phases for each COUT signal application.
HPTZC: For 1-track jumps
Fast phase COUT signal generation with a fast phase TZC signal. (The TZC phase is advanced
by a cut-off 1kHz digital HPF; when MCK = 128Fs.)
STZC:For COUT signal generation when MIRR is externally input and for applications other than
COUT generation
This is generated by sampling the TE signal at 700kHz. (when MCK = 128Fs)
DTZC: For high-speed traverse
Reliable COUT signal generation with a delayed phase STZC signal.
Since it takes some time to generate the MIRR signal, it is necessary to delay the TZC signal in accordance
with the MIRR signal delay during high-speed traverse.
The COUT signal output method is switched with D15 and D14 of $3C.
When D15 = 1: STZC
When D15 = 0 and D14 = 0: HPTZC
When D15 = 0 and D14 = 1: DTZC
When DTZC is selected, the delay can be selected from two values with D14 of $36.
§5-14. Serial Readout Circuit
The following measurement and adjustment results can be read out from the SENS pin by inputting the
readout clock to the SCLK pin by serial command $39. (See Fig. 5-18, Table 5-19 and "Description of SENS
Signals".)
Specified commands
$390C: VC AVRG measurement result
$3908: FE AVRG measurement result
$3904: TE AVRG measurement result
$391F: RF AVRG measurement result
· · ·
· · ·
t
DLS
t
SPW
1/f
SCLK
MSB
LSB
XLAT
SCLK
Serial readout data
(SENS)
Item
Symbol
Min.
Typ.
Max.
Unit
SCLK frequency
SCLK pulse width
Delay time
f
SCLK
t
SPW
t
DLS
31.3
15
16
MHz
ns
μs
Table 5-19.
During readout, the upper 8 bits of the command register must be 39 (Hex).
Fig. 5-18.
$3953: FCS AGCNTL coefficient result
$3963: TRK AGCNTL coefficient result
$391C: TRVSC adjustment result
$391D: FBIAS register value
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相關(guān)代理商/技術(shù)參數(shù) |
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| CXD2598Q | 制造商:SONY 制造商全稱(chēng):Sony Corporation 功能描述:CD Digital Signal Processor with Built-in Digital Servo and DAC |
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| CXD2720Q-2 | 制造商:SONY 制造商全稱(chēng):Sony Corporation 功能描述:Single-Chip Dolby Pro Logic Surround Decoder |
| CXD2721Q-1 | 制造商:SONY 制造商全稱(chēng):Sony Corporation 功能描述:Single-Chip Digital Signal Processor for Karaoke |
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