- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378985 > CXD2588R (Sony Corporation) CD Digital Signal Processor with Built-in Digital Servo and DAC PDF資料下載
參數(shù)資料
| 型號(hào)： | CXD2588R |
| 廠商： | Sony Corporation |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | CD Digital Signal Processor with Built-in Digital Servo and DAC |
| 中文描述： | CD數(shù)字信號(hào)處理器，具有內(nèi)置數(shù)字伺服和DAC |
| 文件頁(yè)數(shù)： | 51/121頁(yè) |
| 文件大小： | 986K |
| 代理商： | CXD2588R |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)當(dāng)前第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)
– 51 –
CXD2588Q/R
§2. Subcode Interface
This section explains the subcode interface.
There are two methods for reading out a subcode externally.
The 8-bit subcodes P to W can be read from SBSO by inputting EXCK to the CXD2588Q/R.
Sub Q can be readout after checking the CRC of the 80 bits in the subcode frame.
Sub Q can be readout from the SQSO pin by inputting 80 clock pulses to the SQCK pin when SCOR comes
correctly and CRCF is high.
§2-1. P to W Subcode Readout
Data can be readout by inputting EXCK immediately after WFCK falls. (See Timing Chart 2-1.)
§2-2. 80-bit Sub Q Readout
Fig. 2-1 shows the peripheral block of the 80-bit Sub Q register.
First, Sub Q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the CRC check
circuit.
96-bit Sub Q is input, and if the CRC is OK, it is output to SQSO with CRCF = 1. In addition, 80 bits are
loaded into the parallel/serial register.
When SQSO goes high 400μs (monostable multivibrator time constant) or more after subcode readout, the
CPU determines that new data (which passed the CRC check) has been loaded.
The CRCF reset is performed by inputting SQCK. When the subcode data is discontinuous after track jump,
etc. CRCF is reset by inputting SQCK. Then, if CRCF =1, the CPU determines that the new data has been
loaded.
When the 80-bit data is loaded, the order of the MSB and LSB is inverted within each byte. As a result,
although the sequence of bytes is the same, the bits within the bytes are now ordered LSB first.
Once the 80-bit data load is confirmed, SQCK is input so that the data can be read.
The SQCK input is detected, and the retriggerable monostable multivibrator is reset while the input is low.
The retriggerable monostable multivibrator has a time constant from 270μs to 400μs. When the duration
when SQCK is high is less than this time constant, the monostable multivibrator is kept reset; during this
interval, the serial/parallel register is not loaded into the parallel/serial register.
While the monostable multivibrator is being reset, data cannot be loaded in the 80-bit parallel/serial register.
In other words, while reading out with a clock cycle shorter than this time constant, the register will not be
rewritten by CRCOK and others. (See Timing Chart 2-2.)
The high and low intervals for SQCK should be between 750ns and 120μs.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CXD2589Q | CD Digital Signal Processor |
| CXD2598Q | CD Digital Signal Processor with Built-in Digital Servo and DAC(數(shù)字式CD信號(hào)處理器（內(nèi)置數(shù)字式伺服系統(tǒng)和D/A轉(zhuǎn)換器）) |
| CXD2598 | CD Digital Signal Processor with Built-in Digital Servo and DAC |
| CXD2719Q | Single-Chip Dolby Pro Logic Surround Decoder(單片杜比環(huán)繞邏輯譯碼器) |
| CXD2720Q | Single-Chip Digital Signal Processor for Karaoke(卡拉OK單片數(shù)字信號(hào)處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CXD2589Q | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CD Digital Signal Processor |
| CXD2597Q | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CD Digital Signal Processor with Built-in Digital Servo and DAC |
| CXD2598 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CD Digital Signal Processor with Built-in Digital Servo and DAC |
| CXD2598Q | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CD Digital Signal Processor with Built-in Digital Servo and DAC |
| CXD2719Q | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Single-Chip Dolby Pro Logic Surround Decoder |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。