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– 43 –
CXD2508AQ/AR
LPWM
(RPWM)
5 4 3
33.8688 [MHZ]
(768Fs)
–5 –4 –3 3 4 5
1.4112 [MHZ] (32Fs)
NLPWM
(NRPWM)
Noise shaper
output value
–3 –4 –5
LPWM
(PRWM)
4 2 0 –2 –4
2.8224 [MHz] (64Fs)
Fig. 4-2.
–4 –2 0 2 4
33.8688 [MHz]
(768Fs)
LPWM
(RPWM)
4 2 0 –2 –4
1.4112 [MHz] (32Fs)
–4 –2 0 2 4
16.9344 [MHz]
(384Fs)
4. 1-bit DAC Block
4-1. PWM Output Pattern
In the CXD2508AQ/AR, PWM outputs from the DAC include forward phase PWM (RPWM, LPWM) and
inverted PWM (NRPWM, NLPWM). By determining the difference between these PWM outputs in the
subsequent analog LPF, the noise and others can be canceled in the digital block. In addition, this method also
yields improvements in the analog characteristics.
The PWM output waveforms differ for each of the CXD2508AQ/AR three playback modes (normal, double-
speed, and pseudo double-speed). (In the following explanation, Fs = 44.1kHz.)
During normal speed playback (DSPB = 0, crystal = 768Fs), eleven values (integers from –5 to 5) are taken
within the 32Fs cycle. The minimum pulse width is –5, and the maximum pulse width is +5. The minimum
variation width of change for PWM is the 384 Fs cycle. (See Fig. 4-3.)
Fig. 4-1.
In double-speed playback (DSPB = 1, crystal = 768Fs), five values (–4, –2, 0, 2, 4) are taken within the 64Fs
cycle. (See Fig. 4-4.)
In pseudo double-speed playback (DSPB = 1, crystal = 384Fs), five values (–4, –2, 0, 2, 4) are taken within the
32Fs cycle. (See Fig. 4-5.)
Fig. 4-3.
4-2. Input Timing for DAC Block
Fig. 4-4 shows the input timing for DAC section.
In the CXD2508AQ/AR, there is no internal transfer of sound data from the CD signal processing block to DAC
block. Therefore, data can be transferred to DAC block through an audio DSP and others.
When data is input to DAC block without passing through an audio DSP or similar device, data should be
connected externally. In that case, EMPH, LRCK, and PCMD can be connected directly with EMPHI, LRCKI,
and PCMDI respectively. (See the Application Circuit.)