
Description
The CXD1265R generates the timing pulses
required by the CCD image sensors as well as
signal processing circuits.
Features
NTSC and PAL compatible
Compatible with digital and analog camera
systems
Black-and-white mode compatible
(EIA/CCIR compatible)
Electronic shutter function
H-driver
Standby function
Compatible with field/frame accumulation
modes
1
,
2
1
Characteristics of CCD image sensor are
guaranteed by field accumulation.
2
Low speed shutter can not be used during frame
accumulation mode.
Applications
CCD cameras
Structure
Silicon gate CMOS IC
Applicable CCD Image Sensors
ICX038BNA, ICX038BNB, ICX038BLA
ICX039BNA, ICX039BNB, ICX039BLA
ICX058AK, ICX058AKB, ICX058AL
ICX059AK, ICX059AKB, ICX059AL
Absolute Maximum Ratings
(Ta = 25°C)
Supply voltage
Input voltage
Output voltage
Operating temperature Topr
Storage temperature
Supply voltage
Allowable power dissipation
V
DD
Vss – 0.5 to +7.0
V
I
Vss – 0.5 to V
DD
+ 0.5 V
V
O
Vss – 0.5 to V
DD
+ 0.5 V
–20 to +75
Tstg
–55 to +150
V
EE
–5 to Vss
V
°C
°C
V
P
D
500
mW
Recommended Operating Conditions
Supply voltage
Operating temperature Topr
V
DD
5.0 ± 0.25
–20 to +75
V
°C
– 1 –
CXD1265R
E92611C52-ST
CCD Camera Timing Generator
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
64 pin LQFP (Plastic)
AAA
AAA
AAA
LATCH
AA
8
15 16 17 18 19 20
21
24 25
28 40
56
4
5
6
7
9
11
12
13
14
23
36
61
22
37
41
42
43
44
45
46
57
59
60
62
GATE
1/2
VD INITIALIZE
SYNC
GEN
3
10
26 27
29
30
39
38
35
34
31 32 33
47 48 49 50 51 52 53
54
55
58
23
HD INITIALIZE
2
64
1
ADR . COUNT
H – ROM
ADR . COUNT
V – ROM
ROG – ROM
MODE
SET
GATE
GATE
DRIVER
HIGH-SPEED
PULSE
GENERATION
CIRCUIT
DECODER
GATE
COUNTER
SHUT
ROM
MICROCOMPUTER
CONTROLLER
63
V
SS
V
DD
HTSG
V
EE
DECODER
Block Diagram