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參數資料
| 型號： | CXA1870 |
| 廠商： | Sony Corporation |
| 元件分類： | 外設及接口 |
| 英文描述： | Single Supply RS232C Line Driver/Receiver(?????μ?o?RS232C ?o?????????¨???2???2??????) |
| 中文描述： | 單電源RS232C接口線路驅動器/接收器（單電源RS232C接口線收發(fā)器（2發(fā)2收）） |
| 文件頁數： | 29/40頁 |
| 文件大?。?/td> | 573K |
| 代理商： | CXA1870 |
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CXA1870S
Description of Operation
1. Synchronizing and picture distortion correction systems
The video signals (2 Vp-p standard) input to Pins 40 and 41 are led to the horizontal and vertical sync
separation circuits for sync separation. The horizontal sync signal is output from Pin 39 with positive
polarity.
This horizontal sync signal is compared with the signal obtained by 1/32 frequency dividing the 32 fH VCO
output using the ceramic oscillator (frequency: 503.5 kHz) to detect a phase difference. The error voltage
resulting from the phase difference is applied to the H oscillator after attenuating the medium and high
frequency components by a lag-lead filter. The phase of the H oscillator output is compared and shifted to
match the phase of the H deflection pulse (flyback pulse) input from Pin 31, and then output from Pin 29.
After the vertical sync signal is synchronized to the input signal by the V countdown system, a sawtooth
wave is generated by charging and discharging the capacitor attached externally to Pin 26. AGC is
performed to ensure that the amplitude of the sawtooth wave is maintained constant regardless of the
vertical frequency of the input, after which the sawtooth wave passes through the picture distortion
correction circuit and is output from Pin 24.
Note that there is no need to adjust the free running frequency for either the H or V oscillator.
When voltage of 3 V or more is applied to Pin 30, the H drive output is held at low level. A time constant
circuit is included to protect against overvoltages, and H drive is output normally when high voltage input
continues for less than 7 V cycles. To release holddown, the IC must be turned off and then started up
again.
Note)
When the external capacitance at Pin 27 is used with 0.1 μF below of recommended value, VD output at
Pin 24 may be unstable. When changing capacitance value, use it more than 0.047 μF.
2. Y/C system
The Y/C system has the following three input systems.
Composite video input (1 Vp-p/2 Vp-p)
2 systems (The gain can be switched between 0 and 6 dB
for both systems.)
1 system
Y/C separation input (2 Vp-p)
The Y signal (specified input level 2 Vp-p) input to Pin 7 is passed through the sub-contrast control, chroma
trap (or delay line), delay line, sharpness control, noise reduction, clamp and auto pedestal circuits. The
signal is then mixed with the color difference signal, passed through the clamp and Y/C MIX circuits again,
and input to the RGB interface system block.
Since a built-in chroma trap is provided, the video signal can be directly input. Trap frequency adjustment
is not necessary as a dummy filter is provided inside the IC and feedback is applied using the 3.58 MHz
signal generated by a crystal oscillator for reference. When the chroma trap is off, the Y system frequency
response is approximately 8 MHz, –3 dB for R, G and B outputs.
Sharpness control is delay line type with a variable PRE/OVER ratio.
Dynamic picture control consists of pulling in the signal below 40 IRE to the black side so that the signal
black peak held by Pin 8 becomes the pedestal level.
The chroma signal (specified input level, burst 570 mVp-p, or video signal 2 Vp-p) input to Pin 9 is passed
through the ACC, TOT, color control (saturation control) and killer detection circuits, after which the burst
locked VCO oscillation output is detected as the carrier. (The detective output LPF is a quadruple.)
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