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參數(shù)資料
| 型號： | CXA1166K |
| 廠商： | Sony Corporation |
| 英文描述： | 8-bit 250 MSPS Flash A/D Converter |
| 中文描述： | 8位250 MSPS的閃存的A / D轉(zhuǎn)換器 |
| 文件頁數(shù)： | 4/28頁 |
| 文件大?。?/td> | 651K |
| 代理商： | CXA1166K |
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– 4 –
CXA1166K
Pin Description
Pin
No.
Symbol
I/O
Standard
voltage level
Equivalent circuit
Description
1
LINV
I
ECL
Polarity selection other than
MSB and overrange.
(Refer to the table of input
voltage vs. Digital output)
Low level is maintained with
left open.
33
MINV
I
ECL
Polarity selection for MSB
(Refer to the table of input
voltage vs. Digital output)
Low level is maintained with
left open.
64
V
RT
I
0V
Reference voltage
(Top) (0V typ.)
65
V
RTS
O
0V
Reference voltage sense
(Top)
52
V
RM
I
V
RB
/2
Reference voltage mid-point.
Can be used for linearity
compensation.
39
V
RBS
O
–2V
Reference voltage sense
(Bottom)
40
V
RB
I
–2V
Reference voltage (Bottom)
54
55
V
IN1
49
50
V
IN2
I
V
RTS
to
V
RBS
Analog input.
Pins 49, 50 and Pins 54, 55
should be connected
externally.
35
CLK
I
ECL
34
CLK
I
ECL
CLK input
Complementary CLK input.
ECL threshold potential
(–1.3V) is maintained with
left open.
The complementary input is
recommended for stable
operation at high speed
though the operation only
with the CLK input is
possible when the CLK
input is left open.
r
r
r
r
LINV
DGND1
DV
EE
–1.3V
MINV
or
18
1
33
28
8
To
Comparator
r2
r
1
r
r
r
r 2
r
4
r
3
r
2
V
RT
V
RM
V
RB
r
5
V
RTS
V
RBS
64
65
25
39
40
AGND
V
IN1
V
IN2
43, 48, 51, 53, 56, 61
128 to 255
To Comp
0 to 127
54
55
49
50
r
r
r
r
r
r
DGND1
18
CLK
35
CLK
34
DV
EE
8
28
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