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參數(shù)資料
| 型號： | CX74038-71 |
| 廠商： | SKYWORKS SOLUTIONS INC |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 2600 MHz, CQCC24 |
| 封裝： | 4.50 X 3.50 MM, 1 MM HEIGHT, CSP-24 |
| 文件頁數(shù)： | 3/17頁 |
| 文件大?。?/td> | 988K |
| 代理商： | CX74038-71 |
Data Sheet I CX74038
Skyworks Solutions, Inc., Proprietary and Confidential
11
101075F
[781] 376-3000 I FAX [781] 376-3100 I SALES@SKYWORKSINC.COM I WWW.SKYWORKSINC.COM
MARCH 7, 2003
Table 6. CX74038 Register Descriptions (1 of 2)
Symbol
Function
Description
Register Word Address 00
Address bits [1:0]
00
SC2
IF synthesizer charge-pump
output current [3:2]
Bit[3:2] selects the IF synthesizer charge pump output
current:
bit 3 bit 2
0
Selects 0.4 mA charge pump output current
0
1
Selects 0.8 mA charge pump output current
1
0
Selects 1.2 mA charge pump output current
1
Selects 1.6 mA charge pump output current
LD
Test mode [6:4]
Bit[6:4] sets the test mode:
bit 6 bit 5 bit 4
0
0 multiplexes Ndiv output of IF SX to LD
output
0
1 multiplexes Rdiv output of IF SX to LD
output
0
1
0 multiplexes lock detect output of IF SX to LD
output
0
1
1 multiplexes ANDed lock detect of both SX to
LD output
1
0
0 multiplexes Ndiv output of RF SX to LD
output
1
0
1 multiplexes Rdiv output of RF SX to LD
output
1
0 multiplexes lock detect output of RF SX to
LD output
1
1 Hi-Zs the charge-pump output of RF SX
R2
IF synthesizer reference divider
[19:7]
Bit[19:7] sets the IF synthesizer 13-bit reference divider ratio
RF synthesizer fractional-N mode
selection [21:20] (Note 1)
Bit[21:20] sets the RF synthesizer fractional-N mode:
bit 21 bit 20
0
Reserved
0
1
Reserved
1
0
Fractional-N mode with dithering
1
Fractional-N mode without dithering
Register Word Address 01
Address bits [1:0]
01
SP1
RF synthesizer phase detector
output polarity [2]
Bit[2] sets the polarity of the RF synthesizer phase detector
output:
0 Sets phase detector output for negative VCO gain
1 Sets phase detector output for positive VCO gain
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