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參數(shù)資料
| 型號： | CX72301-11 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Spur-Free, 1.0 GHz Dual Fractional-N Frequency Synthesizer |
| 中文描述： | 支線免費(fèi)，1.0 GHz雙分?jǐn)?shù)N頻率合成器 |
| 文件頁數(shù)： | 10/20頁 |
| 文件大小： | 165K |
| 代理商： | CX72301-11 |
DATA SHEET CX72301
Skyworks Solutions, Inc. Phone [781] 376-3000 Fax [781] 376-3100 sales@skyworksinc.com www.skyworksinc.com
July 21, 2004 Skyworks Proprietary and Confidential information Products and Product Information are Subject to Change Without Notice 101090H
10
up is 0, signifying that the reference frequency is not divided for
the auxiliary phase detector.
The Control Register allows control of the gain for both phase
detectors and configuration of the LD/PSmain and LD/PSaux pins
for frequency power steering or lock detection. As shown in
Figure 12, the values to be loaded are:
Main Phase Detector Gain = 5-bit value for programmable main
phase detector gain. Range is from 0 to 31 decimal for 31.25 to
1000
μ
A/2
π
radian, respectively.
Main Power Steering Enable = 1-bit value to enable the
frequency power steering circuitry of the main phase detector.
When this bit is a 0, the LD/PSmain pin is configured to be a
lock detect, active-low, open collector pin. When this bit is a 1,
the LD/PSmain pin is configured to be a frequency power
steering pin and can be used to bypass the external main loop
filter to provide faster frequency acquisition.
Auxiliary Phase Detector Gain = 5-bit value for programmable
auxiliary phase detector gain. Range is from 0 to 31 decimal for
31.25 to 1000
μ
A/2
π
radian, respectively.
Auxiliary Power Steering Enable = 1-bit value to enable the
frequency power steering circuitry of the auxiliary phase
detector. When this bit is a 0, the LD/PSaux pin is configured to
be a lock detect, active-low, open collector pin. When this bit is
a 1, the LD/PSaux pin is configured to be a frequency power
steering pin and may be used to bypass the external auxiliary
loop filter to provide faster frequency acquisition.
A3
A2 A1
A0
11
10
9
8
7
6
5
4
3
2
1
0
0
0
1
1
X
X
X
MSB
LSB
Auxiliary Synthesizer Divider Index
C1420
Figure 9. Auxiliary Divider Register (Write Only)
A3
A2 A1
A0
11
10
9
8
7
6
5
4
3
2
1
0
0
1
0
0
X
X
MSB
LSB
Auxiliary Synthesizer Dividend
C1421
Figure 10. Auxiliary Dividend Register (Write Only)
Table 2. Programming the Main Reference Frequency Divider
Decimal
Bit 4 (MSB)
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
Reference Divider
Ratio
0
0
0
0
0
0
1
1
0
0
0
0
1
2
2
0
0
0
1
0
3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31
1
1
1
1
1
32
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