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參數(shù)資料
| 型號： | CVE2 |
| 英文描述： | CVE2 NTSC/PAL Video Encoder Product Brief |
| 中文描述： | CVE2 NTSC / PAL視頻編碼器產(chǎn)品簡介 |
| 文件頁數(shù)： | 1/2頁 |
| 文件大?。?/td> | 95K |
| 代理商： | CVE2 |
CVE2
Product Brief
Tel 408.919.4111
Fax 408.919.4122
www.zoran.com
06/02-LD
Zoran Corporation
3112 Scott Boulevard
Santa Clara, CA 95054-3317
Features
Encodes YCrCb into NTSC or PAL/SECAM
Supports Macrovision 7.1.L1 copy protection
Supports all variations of NTSC encoding
Supports all variations of PAL encoding
(I, B, G, D, N, M and combination N)
RGB SCART output with (MV)
Component YUV output with (MV)
Controlled (smooth) edges on Sync and Burst
Adheres to CCIR 601, 604 and 656 specs; also adheres to
SMTPE 253 spec
Programmable Notch Filter
Upsampled design minimizes sinx/x distortion and complexity
of external analog filter
Nominal sample rate is 27 Msample/s
Advanced Trick Play Features including Zoom,
Smooth Scan
Flexible input configuration: can be timing slave or master
Outputs 10 bit data to DACs
Generic register programming port
Controlled entry and exit of active video line
Fully programmable RGB setup and sync
WSS & CGMS Data Line Encoding
C
VE2-PB-
3
.0
Applications
PC Video
Digital camera process
PC Graphic
Any system requiring TV output
Description
The Zoran NTSC/PAL encoder core continues a line of highly effi-
cient, cost effective solutions for the digital video market. The CVE2
core encodes YCrCb video into all NTSC and PAL standards with
full programmable timing parameters. The carrier frequency and
phase provides maximum flexibility. The core also includes support
for Macrovision 7.1.L1, the copy protection used by DVD and set -
top boxes.
This synthesizable intellectual property core accepts YCrCv video as
specified by the CCIR-601 standard or full range YCrCb. All timing
signals are generated within the core, synchronized to an external
27 MHz clock. In master mode the core provides Hblank and Vblank
to the video source. In slave mode Hblank and Vblank are inputs. In
slave mode the core can also be configured to accept multiplexed
YCrCb as specified by the CCIR-656 standard.
The outputs are 6 separate busses for Y, Composite, Chroma, and
RGB. This allows for flexibility in connection and multiplexing to
DACs.
Design Considerations
Low silicon area: approximately 29,000 gates
Fully synchronous design
Technology independent
;
synthezable to most CMOS libraries
Deliverables
Compilable RTL source code
Bit accurate C model
Synopsis synthesis scripts
Test input files
IP core documentation
CVE2 NTSC/PAL E
ncoder
Solutions on a chip for enjoying the digital life style
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