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參數(shù)資料
| 型號： | CVD1 |
| 廠商： | Zoran Corporation |
| 英文描述： | NTSC/PAL Decoder Intellectual Property Core(NTSC/PAL解碼器智能核心) |
| 中文描述： | 的NTSC / PAL解碼器知識產(chǎn)權(quán)的核心（的NTSC / PAL解碼器智能核心） |
| 文件頁數(shù)： | 1/2頁 |
| 文件大?。?/td> | 55K |
| 代理商： | CVD1 |
CVD1
October 1999
ZR4HCVD1-PB-2.0
PRODUCT BRIEF
NTSC/PAL DECODER INTELLECTUAL PROPERTY CORE
FEATURES
I
Decodes NTSC, PAL or SECAM video into YUV 4:2:2
I
Digital video output
I
Accepts up to 10-bit inputs from ADCs for high quality video
I
Decodes all variations of NTSC video
I
Decodes all variations of PAL
(I, B, G, H, D, N, M, combination N)
I
Requires only two ADCs and two line buffers
I
Adaptive 3 - line comb filter for NTSC & PAL
I
Adaptive 5 - line comb filter for Pal (optional)
I
Clock input range from 20 to 30 MHz
I
Time - base correction
I
Control port clock independent from master video clock
I
Quick time -to- market design turnaround
I
Process technology independent design
I
CCIR 601 on square pixel output
I
Interface to VCO/PLL for continuous clock output
I
Generic R/W port for programming of control registers
I
Automatically detects and notifies presence of Macrovision
signal and decodes in its presence
I
Autodetect of video standard
I
Autodetect and lock VCR trick mode
I
Low power consumption
APPLICATIONS
I
Set-top Box
I
PC Graphics Chips
I
Video Editing
I
Desktop Video Capture
I
Video Conferencing and Video Phones
I
Digital TV
DESCRIPTION
The Zoran NTSC/PAL/SECAM video decoder core (CVD1) is
an area efficient, high image quality, cost effective solution for
digital video system-on-a-chip applications. The CVD1 core
decodes NTSC/PAL/SECAM composite or Y/C video and
converts it into YUV 4:2:2 16-bit digital video.
Design Considerations
Fully synchronous area efficient design - less than 90,000
gates
Technology independent. Can be synthesized in any
0.5μm. 0.35μm, or 0.25μm CMOS library
Deliverables
RTL source code
PLI routines for synopsis VL5 or Verilog X L
Synopsis synthesis scripts
Bit accurate C Model
Test input files
Documentation
Golden simulation result files
FPGA evaluation board
Figure 1. CVD1 Core
Variable gain
amplifier and
DC offset
ADC
Register file
H PLL
Adaptive 3
tap comb
NTSC PAL
SECAM
demodulator
C PLL
Y
Cr/Cb
H, V,
Hblank
etc
Analog
front
control
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