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參數(shù)資料
| 型號： | CT2566 |
| 廠商： | Aeroflex Inc. |
| 英文描述： | CT2566 MIL-STD-1553 to Microprocessor Interface Unit |
| 中文描述： | CT2566的MIL - STD - 1553的微處理器接口單元 |
| 文件頁數(shù)： | 4/37頁 |
| 文件大?。?/td> | 326K |
| 代理商： | CT2566 |
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Aeroflex Circuit Technology
SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700
4
28
29
D01
SSFLAG
I/O
O
Data Bus Bit 1.
Subsystem Flag. Output to 1553 device to set RT subsystem
flag status bit.
Subsystem Busy. Output to 1553 device to set RT subsystem
busy flag.
Output to 1553 device used in conjunction with MT to set
operating mode.
Address Bit 14.
Address Bit 12.
Address Bit 10.
Address Bit 8.
Address Bit 6.
Address Bit 4.
Address Bit 2.
Address Bit 0 (LSB).
Signal Return.
Strobe Data. Used in conjunction with SELECT to indicate a
data transfer cycle to/from CPU.
Input/Output Enable. Output from CT2566 to enable external
buffers/latches connecting the hybrid to the address/data
bus.
External Load. Used to load data into external device via the
CT2566 data bus. Same timing as MEMWR.
Input from 1553 in RT mode used to indicate received 1553
message came in either Channel A or B.
Interrupt. Interrupt pulse line to CPU.
Bus Controller Start. Outputs to 1553 in initiate BC cycle.
Reset. Output to external device from CT2566 consisting of
the OR condition of CPU reset and CPU Master Clear.
Message Error. Input from 1553 device when an error occurs
in message sequence.
Input to change active memory map area (0 = area A).
Output from CT2566 selecting which area is to be active (0 =
area A).
Input from 1553 device indicating no response time-out.
Master Clear. Power-on reset from CPU. Resets DMA in
progress and internal registers to logic “0”.
Bus Acknowledge. Input from 1553 device acknowledge
receipt of BUSGRNT.
Write. Input from 1553 device for writing data into memory.
Chip Select. Input from 1553 device that is routed to
MEMCS.
30
SSBUSY
O
31
RTU/BC
O
32
33
34
35
36
37
38
39
40
41
A14
A12
A10
A08
A06
A04
A02
A00
GND
STRBD
O
O
O
O
O
O
I/O
I/O
-
I
42
IOEN
O
43
EXTLD
O
44
CHB/CHA
45
46
47
INT
BCSTART
RESET
O
O
O
48
MSGERR
I
49
50
CTLIN B/A
CTLOUT B/A
I
O
51
52
TIMEOUT
MSTRCLR
I
I
53
BUSACK
I
54
55
WR
CS
I
I
PIN NO.
NAME
I/O
DESCRIPTION
Table 2 – Pin Functions (78 Pin DIP) (Cont.)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CT2566-FP | CT2566 MIL-STD-1553 to Microprocessor Interface Unit |
| CT2577 | APPLICATION NOTE #108 |
| CT2579 | APPLICATION NOTE #108 |
| CT2581-02-IN-F84 | CT2578 / CT2581 SIMPLE REMOTE TERMINAL FOR MIL-STD-1553 / 1760 & McAir |
| CT2581-02-IN-P119 | CT2578 / CT2581 SIMPLE REMOTE TERMINAL FOR MIL-STD-1553 / 1760 & McAir |
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