參數(shù)資料
型號: CT2554
廠商: Aeroflex Inc.
英文描述: CT2553 / 2554 / 2555 / 2556 Advanced Integrated MUX (AIM) Hybrid FOR MIL-STD-1553
中文描述: CT2553 / 2554 /二千五百五十六分之二千五百五十五高級集成復(fù)用器(AIM)的混合的MIL - STD - 1553的
文件頁數(shù): 31/36頁
文件大小: 352K
代理商: CT2554
Aeroflex Circuit Technology
31
SCDCT2553 REV B 8/6/99 Plainview NY (516) 694-6700
Table 7A – CT2553 Pin Function Table (78 Pin DIP)
Pin
Name
I
IH
(μA)
I
IL
(mA) I
OH
(μA) I
OL
(mA)
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
D00
D02
D04
D06
D08
D10
D12
D14
RTAD1
RTAD0
RTAD4
ILLCMD
SA/MC-0
(5)
(5)
(5)
(5)
(5)
(5)
(5)
(5)
(5)
(5)
(5)
+10
-
-0.4
-0.4
-0.4
-0.4
-0.4
-0.4
-0.4
-0.4
-0.4
-0.4
-0.4
±0.01
-
-400
-400
-400
-400
-400
-400
-400
-400
-
-
-
-
-400
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
-
-
-
-
2.0
I/O Data Bus Bit 0 (LSB).
I/O Data Bus Bit 2.
I/O Data Bus Bit 4.
I/O Data Bus Bit 6.
I/O Data Bus Bit 8.
I/O Data Bus Bit 10.
I/O Data Bus Bit 12.
I/O Data Bus Bit 14.
Remote Terminal Address Bit 1.
Remote Terminal Address Bit 0 (LSB)
Remote Terminal Address Bit 4 (MSB)
Legal Command. Defines the received command as illegal.
Subaddress/Mode Command Bit 0. Multiplexed output bit-0 of
subaddress/word count field of the current command word. SA/MC
determined by the state of LMC.
+5V supply input for digital logic section. B6 counter.
Subaddress/Mode Command Bit 1. In MT mode, pulses every time 32
words have been stored. B7 counter.
Broadcast Received. Indicates current command is a 1553 Broadcast
Command.
Latched Mode Command. Logic 1 indicates current command word is a
mode code and selects MC0-MC4. Logic 0 indicates non-mode
comrnand and selects SA0-SA4.
-15V input power supply connection for the B channel transceiver.
Ground B. Power supply return connection for the B channel
transceiver.
Transmit/Receive transceiver-B. Input/output to the coupling
transformer that connects to the B channel of the 1553 Bus.
Logic Ground. Power supply return for the digital logic section.
Address Bit 1
Address Bit 3
Address Bit 5
Address Bit 7
Address Bit 9
Address Bit 11
Address Bit 13
Address Bit 15 (MSB)
Memory Output Enable. A Logic 0 used to enable data output
from memory when
the 1553 or CPU reads from memory.
Memory Enable Out. Low level output to enable external RAM.
Used with MEMOE
to read data or with MEMWR to write data into
external RAM.
Clock Input. 16 MHz TTL clock.
Memory/Register. Input from CPU to select memory or register data
transfer.
Strobe Data. Used in conjunction with SELECT to initiate a data
transfer cycle
to/from CPU.
External Enable. Used to load data into external devices.
Read/Write. Input from the CPU which defines the Data Bus
transfer as a read
or write operation.
External load. Used to load data into external devices.
Ground A. Power supply return connection for the A channel
transceiver.
-I5V input power supply connection for the A channel transceiver.
Transmit/Receive transceiver-A. Input/Output to the coupling
transformer that connects
to the A channel of the 1553 Bus.
I/O Data Bus Bit 1.
I/O Data Bus Bit 3.
I/O Data Bus Bit 5
I/O Data Bus Bit 7.
14
15
Logic +5V
SA/MC-1
-
-
-
-
-
-
-400
2.0
16
BCSTRCV
-
-
-400
2.0
17
LMC
-
-
-400
2.0
18
19
-15V
GNDB
-
-
-
-
-
-
-
-
20
TX/RX-B
-
-
-
-
21
22
23
24
25
26
27
28
29
30
Logic GND
A01
A03
A05
A07
A09
A11
A13
A15
MEMOE
-
-
-
-
(5)
(5)
(5)
(5)
(5)
(5)
(5)
(5)
-0.4
-0.4
-0.4
-0.4
-0.4
-0.4
-0.4
-0.4
-400
-400
-400
-400
-400
-400
-400
-400
-400
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
4.0
31
MEMENA-OUT
-
-
-400
4.0
32
33
CLOCK IN
MEM/REG
±20
(6)
±0.02
-0.7
-
-
-
-
34
STRBD
(6)
-0.7
-
-
35
36
EXTEN
RD/WR
-
-
(6)
-0.7
-
-
37
38
EXTLD
GNDA
-
-
-
-
-
-
39
40
-15VA
TX/RX-A
-
-
-
-
-
-
-
-
41
42
43
44
D01
D03
D05
D07
(5)
(5)
(5)
(5)
-0.4
-0.4
-0.4
-0.4
-400
-400
-400
-400
3.6
3.6
3.6
3.6
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