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參數(shù)資料
| 型號： | CT2500 |
| 廠商： | Aeroflex Inc. |
| 英文描述： | CT2500 MIL-STD-1397 Type D & E Low Level Serial Interface Protocol Chip |
| 中文描述： | CT2500的MIL - STD - 1397 D型 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 144K |
| 代理商： | CT2500 |
Aeroflex Circuit Technology
SCDCT2500 REV A 6/12/98 Plainview NY (516) 694-6700
3
I/O FUNCTION LISTING
NAME
I/O
DESCRIPTION
SO/SI
I
Source / Sink Mode Select
Determines the overall Functioning Mode of the Device.
"1"= Source emulation. This mode enables the chip to send control frames, single
command and data words and burst data. It is able to receive control frames.
"0" = Sink emulation. In this mode, the chip can only send control frames. It can
receive control frames, command words, single data words and burst data.
DO-D31
I/O
Parallel Bi-directional Data Bus (Internal Pullups)
Source Mode
: Input to 32 bit transmit data latch
Sink Mode
: Tri-state output from 32 bit received data latch
D/E
I
Type D / Type E Control Frame Length Select (Internal Pulldown)
"1" = Three bit control frames are transmitted and the received control frame is
checked for a proper three bit length.
"0" = Four bit control frames are transmitted and the received control frame is checked
for a proper four bit length.
PAREN
I
Parity Enable (Internal Pullup)
"1" = Parity bit is generated in Source mode and checked for in Sink mode.
"0" = No parity is generated or checked for.
POE
I
Parity Odd or Even Select (Internal Pullup)
"1" = Odd parity
"0" = Even parity
CLK
I
System Clock
20 megahertz with 50% duty cycle
BURST
I
Burst Mode Select
"1" = Data transmission and Reception can be done in Burst mode
"0" = Normal operation
Source Mode
: Data words loaded during the transmission of another will be
concatenated to the transmission without addition of SYNC or WI bits. The first word
will have a SYNC bit of "1" and and a WI bit, which must be set to "0". The Burst line
must remain stable for the entire duration of the loading and transmission of the data.
Sink Mode
: During a Burst data reception, after the SYNC and WI bits, data words are
picked off at bit count multiples of 32, or 33 with parity enabled, and loaded into the
output latch. The transmission is considered ended when a gap is detected. The line
must be stable during the entire reception.
STR1 and
STR2
I
Strobe One Bar and Strobe Two Bar
Control Strobes for Reading and Writing the Parallel I/O data Latches
Source Mode
: STR1 loads data present on DO-D15 into the lower 16 bit input latch
and STR2 loads data on D16-D31 into the upper 16 bit input latch. Upon completion of
STR2, a sequence is initiated to load the entire 32 bits into a shift register and start a
transmission. The lower 16 bits must be loaded prior to or during the load of the upper
16 bits. For a 32 bit load, STR1 and STR2 can be tied together.
Sink Mode
: STR1 enables the lower 16 bits of a received word to be output on
D0-D15. STR2 enables the upper 16 bits of a received word to be output on D16-D31.
The entire 32 bits of data must be read before another data reception or it will be
overwritten. If this occurs, the overflow flag, OVRFLOW, will go high. The data is
considered completely read upon the completion of STR2.
CMDIN
O
Command In
Third bit of the Received Control Frame. Valid during RCVCNTRL.
DTAIN
O
Data In
Second bit of the Received Control Frame. Valid during RCVCNTRL.
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