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參數(shù)資料
| 型號： | CT1815 |
| 廠商： | Aeroflex Inc. |
| 英文描述： | CT1815 10MHz Low Level Serial Interface for MIL-STD-1397 Type D |
| 中文描述： | CT1815 10MHz的串行接口低級別的MIL - STD - 1397 D型 |
| 文件頁數(shù)： | 5/7頁 |
| 文件大?。?/td> | 81K |
| 代理商： | CT1815 |
Aeroflex Circuit Technology
SCDCT1815 REV A 6/12/98 Plainview NY (516) 694-6700
5
Functional Description and Pinout
Pin
#
1
2
3
Pin Name
Function
Load or
Drive
No connection
No connection
XFMR secondary/
RX data input
Test Point
Test Point
Test Point
-5 Volts
R
X
strobe
Power management
input
Encoder enable
Case/signal GND
Case/signal GND
Decoded data
envelope
TP3 test point
TP1 test point
TP2 test point
-5 Volts
TP4 test point
Clock
R
No connection
Decoded Data
R
No connection
+5 volts
+5 volts
10 MHz encoder shift
clock
NRZ serial input data
Encode envelope
Transmitter-receiver I/O pin
4
5
6
7
8
9
No connection permitted
No connection permitted
No connection permitted
Low level disables receiver
Controls transmitter power consumption in conjunction with pin 10
3 S loads
1 S load
10
11
12
13
Controls transmitter power consumption in conjunction with pin 9
1 S load
High after reception of first half bit; goes low after reception of last
half bit (normally low in inactive state)
Alignment point: no electrical connection permitted
Alignment point: no electrical connection permitted
Alignment point: no electrical connection permitted
4 S drive
14
15
16
17
18
19
20
21
22
23
24
25
Alignment point: no electrical connection permitted
Reconstructed clock; one clock pulse per input bit received
3 S drive
NRZ reconstructed data. Sampled on clock
R
rising edge
3 S drive
One cycle required per data bit. Must be high in first half of bit cell
1 S load
26
27
Serial input to be Manchester encoded with the 20 MHz gated CK
Must be high to enable transmission; must go low before reception
of last 20 MHz positive edge to complete transmission
Each bit to be encoded requires two positive edges of the 20 MHz
CK. These edges must occur at 25ns and 75ns into the bit cell.
The end of transmission requires an additional edge in conjunction
with a logic low on the encode envelope. t
R
, t
F
< 5nsec.
Logic low resets encoder
1 S load
1 S load
28
20 MHz gated clock
(encoder)
1 S load
29
Master reset
reset pulse <15 nsec
No connection
No connection
XFMR secondary/
RX DATA input
XFMR secondary
XFMR primary/
TX DATA output
2 S load
30
31
32
Transmitter-Receiver I/O pin
33
34
Secondary isolated winding, same phase as outer conducter
Transformer lead for connection to outer conductor of tri-axial
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