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參數(shù)資料
| 型號(hào)： | CT1698FP |
| 廠商： | Aeroflex Inc. |
| 英文描述： | CT1698 MIL-STD-1397 Type E 10MHz Low Level Serial Interface |
| 中文描述： | CT1698的MIL - STD - 1397 E型10MHz的串行接口低級(jí)別 |
| 文件頁(yè)數(shù)： | 5/7頁(yè) |
| 文件大?。?/td> | 82K |
| 代理商： | CT1698FP |
Aeroflex Circuit Technology
SCDCT1698 REV A 6/12/98 Plainview NY (516) 694-6700
5
Drive Level Control Pins
External Resistors may be connected from pins 5 and 6 to V
EE
or GND to change the Transmitter Output
Level. If pins 5 and 6 are left open the CT1698 operates within the MIL-STD-1397 Type E specification.
Resistors connected from pins 5 and 6 to V
EE
or Ground must be equal. Unequal resistors will result in a
transmitter output offset level.
The formula for peak to peak transmitter output swing with resistors connected between 5 and 6 to V
EE
is:
The formula for peak to peak transmitter output swing with resistors connected between pins 5 and 6 to
ground is:
Functional Description and Pinout
Pin
#
Pin Name
Function
Load or
Drive
1
XFMR primary/
TX data output
XFMR secondary
TXDATA output/
RX data input
No connection
Drive 2
Drive 1
-5 Volts
R
X
strobe
Power management
input
Encoder enable
Case/signal GND
Case/signal GND
Decoded data
envelope
TP3 test point
TP1 test point
TP2 test point
-5 Volts
TP4 test point
Clock
R
No connection
Decoded Data
R
Transformer lead for connection to center conductor of tri-axial
cable
Secondary isolated winding, same phase as center conductor
Transmitter-receiver I/O pin (usually connected to pin 2)
2
3
4
5
6
7
8
9
Output level adjustment selected by resistor to GND or V
EE
Output level ajustment selected by resistor to GND or V
EE
Low level disables receiver
Controls transmitter power consumption in conjunction with pin 10
3 S loads
1 S load
10
11
12
13
Controls transmitter power consumption in conjunction with pin 9
1 S load
High after reception of first half bit; goes low after reception of last
half bit (normally low in inactive state)
Alignment point: no electrical connection permitted
Alignment point: no electrical connection permitted
Alignment point: no electrical connection permitted
4 S drive
14
15
16
17
18
19
20
21
Alignment point: no electrical connection permitted
Reconstructed clock; one clock pulse per input bit received
3 S drive
NRZ reconstructed data. Sampled on clock
R
rising edge
3 S drive
V
OUpk-pk
= 1.39 + 125 ± 15% Volts, R
EXT
> 90
R
EXT
V
OUpk-pk
= 1.39 - 50 (V
EE
-2.5) ± 15% Volts, R
EXT
> 180
R
EXT
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