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參數(shù)資料
| 型號(hào)： | CSPDDR100 |
| 廠商： | California Micro Devices Corporation |
| 英文描述： | CHIP SCALE DDR TERMINATION ARRAY |
| 中文描述： | 芯片級(jí)DDR終端陣列 |
| 文件頁數(shù)： | 1/4頁 |
| 文件大?。?/td> | 55K |
| 代理商： | CSPDDR100 |
2000 California Micro Devices Corp. All rights reserved.
7/21/2000
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CSPDDR100
CALIFORNIA MICRO DEVICES
215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
Chip Scale DDR Termination Array
Features
16 Integrated High frequency Series/Parallel
Terminations
Ultra small footprint Chip Scale Package
Ceramic substrate
0.35mm Eutectic Solder Bumps, 0.65mm Pitch
Product Description
The CSPDDR100 is a high performance Integrated
Passive Device (IPD) which provides Series/Parallel
terminations suitable for use in SSTL and DDR termina-
tion applications. Sixteen (16) Series/Parallel termination
channels are provided for a total of 32 integrated
resistors. These resistors provide excellent high fre-
quency performance in excess of 3GHz and are manu-
factured to an absolute tolerance of ±1%. The Chip
Applications
DDR Memory bus termination
SSTL Termination
C1260700
SCHEMATIC DIAGRAM
Scale Package provides an ultra small footprint for
this Integrated Passive Device and provides minimal
parasitics compared to conventional packaging. Typical
bump inductance is less than 25pH. The large solder
bumps and ceramic substrate allow for standard attach-
ment to laminate printed circuit boards without the use
of underfill. The 4X9 Bump pattern is arranged for easy
flow through routing on the pcb.
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